2,058 research outputs found
Superlattice Nanowire Pattern Transfer (SNAP)
During the past 15 years or so, nanowires (NWs) have emerged as a new and distinct class of materials. Their novel structural and physical properties separate them from wires that can be prepared using the standard methods for manufacturing electronics. NW-based applications that range from traditional electronic devices (logic and memory) to novel biomolecular and chemical sensors, thermoelectric materials, and optoelectronic devices, all have appeared during the past few years. From a fundamental perspective, NWs provide a route toward the investigation of new physics in confined dimensions.
Perhaps the most familiar fabrication method is the vapor−liquid−solid (VLS) growth technique, which produces semiconductor nanowires as bulk materials. However, other fabrication methods exist and have their own advantages.
In this Account, I review a particular class of NWs produced by an alternative method called superlattice nanowire pattern transfer (SNAP). The SNAP method is distinct from other nanowire preparation methods in several ways. It can produce large NW arrays from virtually any thin-film material, including metals, insulators, and semiconductors. The dimensions of the NWs can be controlled with near-atomic precision, and NW widths and spacings can be as small as a few nanometers. In addition, SNAP is almost fully compatible with more traditional methods for manufacturing electronics. The motivation behind the development of SNAP was to have a general nanofabrication method for preparing electronics-grade circuitry, but one that would operate at macromolecular dimensions and with access to a broad materials set. Thus, electronics applications, including novel demultiplexing architectures; large-scale, ultrahigh-density memory circuits; and complementary symmetry nanowire logic circuits, have served as drivers for developing various aspects of the SNAP method. Some of that work is reviewed here.
As the SNAP method has evolved into a robust nanofabrication method, it has become an enabling tool for the investigation of new physics. In particular, the application of SNAP toward understanding heat transport in low-dimensional systems is discussed. This work has led to the surprising discovery that Si NWs can serve as highly efficient thermoelectric materials. Finally, we turn toward the application of SNAP to the investigation of quasi-one-dimensional (quasi-1D) superconducting physics in extremely high aspect ratio Nb NWs
Understanding the interaction between energetic ions and freestanding graphene towards practical 2D perforation
We report experimentally and theoretically the behavior of freestanding
graphene subject to bombardment of energetic ions, investigating the ability of
large-scale patterning of freestanding graphene with nanometer sized features
by focused ion beam technology. A precise control over the He+ and Ga+
irradiation offered by focused ion beam techniques enables to investigate the
interaction of the energetic particles and graphene suspended with no support
and allows determining sputter yields of the 2D lattice. We find strong
dependency of the 2D sputter yield on the species and kinetic energy of the
incident ion beams. Freestanding graphene shows material semi-transparency to
He+ at high energies (10-30 keV) allowing the passage of >97% He+ particles
without creating destructive lattice vacancy. Large Ga+ ions (5-30 keV), in
contrast, collide far more often with the graphene lattice to impart
significantly higher sputter yield of ~50%. Binary collision theory applied to
monolayer and few-layer graphene can successfully elucidate this collision
mechanism, in great agreement with experiments. Raman spectroscopy analysis
corroborates the passage of a large fraction of He+ ions across graphene
without much damaging the lattice whereas several colliding ions create single
vacancy defects. Physical understanding of the interaction between energetic
particles and suspended graphene can practically lead to reproducible and
efficient pattern generation of unprecedentedly small features on 2D materials
by design, manifested by our perforation of sub-5-nm pore arrays. This
capability of nanometer scale precision patterning of freestanding 2D lattices
shows practical applicability of the focused ion beam technology to 2D material
processing for device fabrication and integration.Comment: 31 pages of main text (with 4 figures) plus 4 pages of supporting
information (with 2 figures). Original article submitted to a journal for
consideration for publicatio
Visible and infrared photocurrent enhancement in a graphene-silicon Schottky photodetector through surface-states and electric field engineering
The design of efficient graphene-silicon (GSi) Schottky junction
photodetectors requires detailed understanding of the spatial origin of the
photoresponse. Scanning-photocurrent-microscopy (SPM) studies have been carried
out in the visible wavelengths regions only, in which the response due to
silicon is dominant. Here we present comparative SPM studies in the visible
( = 633nm) and infrared ( = 1550nm) wavelength regions for a
number of GSi Schottky junction photodetector architectures, revealing the
photoresponse mechanisms for silicon and graphene dominated responses,
respectively, and demonstrating the influence of electrostatics on the device
performance. Local electric field enhancement at the graphene edges leads to a
more than ten-fold increased photoresponse compared to the bulk of the
graphene-silicon junction. Intentional design and patterning of such graphene
edges is demonstrated as an efficient strategy to increase the overall
photoresponse of the devices. Complementary simulations and modeling illuminate
observed effects and highlight the importance of considering graphene's shape
and pattern and device geometry in the device design
Integration of Bulk Piezoelectric Materials into Microsystems.
Bulk piezoelectric ceramics, compared to deposited piezoelectric thin-films, provide greater electromechanical coupling and charge capacity, which are highly desirable in many MEMS applications. In this thesis, a technology platform is developed for wafer-level integration of bulk piezoelectric substrates on silicon, with a final film thickness of 5-100μm. The characterized processes include reliable low-temperature (200˚C) AuIn diffusion bonding and parylene bonding of bulk-PZT on silicon, wafer-level lapping of bulk-PZT with high-uniformity (±0.5μm), and low-damage micro-machining of PZT films via dicing-saw patterning, laser ablation, and wet-etching. Preservation of ferroelectric and piezoelectric properties is confirmed with hysteresis and piezo-response measurements. The introduced technology offers higher material quality and unique advantages in fabrication flexibility over existing piezoelectric film deposition methods.
In order to confirm the preserved bulk properties in the final film, diaphragm and cantilever beam actuators operating in the transverse-mode are designed, fabricated and tested. The diaphragm structure and electrode shapes/sizes are optimized for maximum deflection through finite-element simulations. During tests of fabricated devices, greater than 12μmPP displacement is obtained by actuation of a 1mm2 diaphragm at 111kHz with <7mW power consumption. The close match between test data and simulation results suggests that the piezoelectric properties of bulk-PZT5A are mostly preserved without any necessity of repolarization.
Three generations of resonant vibration energy harvesters are designed, simulated and fabricated to demonstrate the competitive performance of the new fabrication process over traditional piezoelectric deposition systems. An unpackaged PZT/Si unimorph harvester with 27mm3 active device volume produces up to 205μW at 1.5g/154Hz. The prototypes have achieved the highest figure-of-merits (normalized-power-density × bandwidth) amongst previously reported inertial energy harvesters.
The fabricated energy harvester is utilized to create an autonomous energy generation platform in 0.3cm3 by system-level integration of a 50-80% efficient power management IC, which incorporates a supply-independent bias circuitry, an active diode for low-dropout rectification, a bias-flip system for higher efficiency, and a trickle battery charger. The overall system does not require a pre-charged battery, and has power consumption of <1μW in active-mode (measured) and <5pA in sleep-mode (simulated). Under 1g vibration at 155Hz, a 70mF ultra-capacitor is charged from 0V to 1.85V in 50 minutes.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/1/aktakka_3.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/2/aktakka_2.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/3/aktakka_1.pd
The role of topology and mechanics in uniaxially growing cell networks
In biological systems, the growth of cells, tissues, and organs is influenced
by mechanical cues. Locally, cell growth leads to a mechanically heterogeneous
environment as cells pull and push their neighbors in a cell network. Despite
this local heterogeneity, at the tissue level, the cell network is remarkably
robust, as it is not easily perturbed by changes in the mechanical environment
or the network connectivity. Through a network model, we relate global tissue
structure (i.e. the cell network topology) and local growth mechanisms (growth
laws) to the overall tissue response. Within this framework, we investigate the
two main mechanical growth laws that have been proposed: stress-driven or
strain-driven growth. We show that in order to create a robust and stable
tissue environment, networks with predominantly series connections are
naturally driven by stress-driven growth, whereas networks with predominantly
parallel connections are associated with strain-driven growth
Closing the Loop on Morphogenesis: A Mathematical Model of Morphogenesis by Closed-Loop Reaction-Diffusion
Morphogenesis, the establishment and repair of emergent complex anatomy by
groups of cells, is a fascinating and biomedically-relevant problem. One of its
most fascinating aspects is that a developing embryo can reliably recover from
disturbances, such as splitting into twins. While this reliability implies some
type of goal-seeking error minimization over a morphogenic field, there are
many gaps with respect to detailed, constructive models of such a process being
used to implement the collective intelligence of cellular swarms. We describe a
closed-loop negative-feedback system for creating reaction-diffusion (RD)
patterns with high reliability. It uses a cellular automaton to characterize a
morphogen pattern, then compares it to a goal and adjusts accordingly,
providing a framework for modeling anatomical homeostasis and robust generation
of target morphologies. Specifically, we create a RD pattern with N
repetitions, where N is easily changeable. Furthermore, the individual
repetitions of the RD pattern can be easily stretched or shrunk under genetic
control to create, e.g., some morphological features larger than others.
Finally, the cellular automaton uses a computation wave that scans the
morphogen pattern unidirectionally to characterize the features that the
negative feedback then controls. By taking advantage of a prior process
asymmetrically establishing planar polarity (e.g., head vs. tail), our
automaton is greatly simplified. This work contributes to the exciting effort
of understanding design principles of morphological computation, which can be
used to understand evolved developmental mechanisms, manipulate them in
regenerative medicine settings, or embed a degree of synthetic intelligence
into novel bioengineered constructs.Comment: 20 pages, 3 tables, 5 figure
A survey of carbon nanotube interconnects for energy efficient integrated circuits
This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design
Process-induced Structural Variability-aware Performance Optimization for Advanced Nanoscale Technologies
Department of Electrical EngineeringAs the CMOS technologies reach the nanometer regime through aggressive scaling, integrated circuits (ICs) encounter scaling impediments such as short channel effects (SCE) caused by reduced ability of gate control on the channel and line-edge roughness (LER) caused by limits of the photolithography technologies, leading to serious device parameter fluctuations and makes the circuit analysis difficult. In order to overcome scaling issues, multi-gate structures are introduced from the planar MOSFET to increase the gate controllability.
The goal of this dissertation is to analyze structural variations induced by manufacturing process in advanced nanoscale devices and to optimize its impacts in terms of the circuit performances. If the structural variability occurs, aside from the endeavor to reduce the variability, the impact must be taken into account at the design level. Current compact model does not have device structural variation model and cannot capture the impact on the performance/power of the circuit. In this research, the impacts of structural variation in advanced nanoscale technology on the circuit level parameters are evaluated and utilized to find the optimal device shape and structure through technology computer-aided-design (TCAD) simulations. The detail description of this dissertation is as follows:
Structural variation for nanoscale CMOS devices is investigated to extend the analysis approach to multi-gate devices. Simple and accurate modeling that analyzes non-rectilinear gate (NRG) CMOS transistors with a simplified trapezoidal approximation method is proposed. The electrical characteristics of the NRG gate, caused by LER, are approximated by a trapezoidal shape. The approximation is acquired by the length of the longest slice, the length of the smallest slice, and the weighting factor, instead of taking the summation of all the slices into account. The accuracy can even be improved by adopting the width-location-dependent factor (Weff). The positive effect of diffusion rounding at the transistor source side of CMOS is then discussed. The proposed simple layout method provides boosting the driving strength of logic gates and also saving the leakage power with a minimal area overhead. The method provides up to 13% speed up and also saves up to 10% leakage current in an inverter simulation by exploiting the diffusion rounding phenomena in the transistors.
The performance impacts of the trapezoidal fin shape of a double-gate FinFET are then discussed. The impacts are analyzed with TCAD simulations and optimal trapezoidal angle range is proposed. Several performance metrics are evaluated to investigate the impact of the trapezoidal fin shape on the circuit operation. The simulations show that the driving capability improves, and the gate capacitance increases as the bottom fin width of the trapezoidal fin increases. The fan-out 4 (FO4) inverter and ring-oscillator (RO) delay results indicate that careful optimization of the trapezoidal angle can increase the speed of the circuit because the ratios of the current and capacitance have different impacts depending on the trapezoidal angle.
Last but not least, the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using device simulations are also investigated in this work. The DGAA FET, a kind of nanotube field-effect transistor (NTFET), can solve the problem of loss of gate controllability of the channel and provide improved short-channel behavior. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, this work proposes the n/p DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional GAA inverter structure. In the optimum structure, 27% propagation delay and 15% leakage power improvement can be achieved.
Analysis and optimization for device-level variability are critical in integrated circuit designs of advanced technology nodes. Thus, the proposed methods in this dissertation will be helpful for understanding the relationship between device variability and circuit performance. The research for advanced nanoscale technologies through intensive TCAD simulations, such as FinFET and GAA, suggests the optimal device shape and structure. The results provide a possible solution to design high performance and low power circuits with minimal design overhead.ope
Integrated Lithographic Molding for Microneedle-Based Devices
This paper presents a new fabrication method consisting of lithographically defining multiple layers of high aspect-ratio photoresist onto preprocessed silicon substrates and release of the polymer by the lost mold or sacrificial layer technique, coined by us as lithographic molding. The process methodology was demonstrated fabricating out-of-plane polymeric hollow microneedles. First, the fabrication of needle tips was demonstrated for polymeric microneedles with an outer diameter of 250 mum, through-hole capillaries of 75-mum diameter and a needle shaft length of 430 mum by lithographic processing of SU-8 onto simple v-grooves. Second, the technique was extended to gain more freedom in tip shape design, needle shaft length and use of filling materials. A novel combination of silicon dry and wet etching is introduced that allows highly accurate and repetitive lithographic molding of a complex shape. Both techniques consent to the lithographic integration of microfluidic back plates forming a patch-type device. These microneedle-integrated patches offer a feasible solution for medical applications that demand an easy to use point-of-care sample collector, for example, in blood diagnostics for lithium therapy. Although microchip capillary electrophoresis glass devices were addressed earlier, here, we show for the first time the complete diagnostic method based on microneedles made from SU-8
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