Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies.In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien

Engineering Approaches for Neurobiology

Neurobiological systems span a wide dimensional range. We present a scale-driven methodological development for three biological systems to demonstrate the utility of applied engineering approaches in neurobiology and provide an avenue for future study. Concepts in computational modeling, microfluidic device platforms, and MRI phantoms are examined - starting from the level of a single synapse and concluding with long-distance cortical connectivity.Single synapse models were developed using a Monte Carlo simulation environment to study biophysically realistic mechanisms of spike timing dependent plasticity (STDP). A model of spatiotemporal intracellular Calcium detection was extended to include subunit-specific receptor kinetics and distributions. Using STDP-based activation protocols, global and local molecular time courses were then produced for NR2a and NR2b knockout models. To study network level oscillatory activity, a model of spatially-constrained networks was created based on cyclic geometry to look at the effects of circumference and track-width on spontaneous network activity. Transverse wave activity is demonstrated and characterized by velocity and origin. Microfluidic technology provides an experimental means to extend the study of network organization and activity in vitro. We have developed a microfluidic control platform that integrates multiple design strategies to address the intrinsic spatiotemporal resolution of neurons. Microfluidic devices were fabricated using multilayer soft-lithography with internal valves to guide multiple laminar streams. A control platform using dynamic pressure produces a targeted hydrodynamic stream from variable internal resistance control. Feedback containing video and pressure data provides online analysis of the microfluidic device. Devices were characterized with arbitrary profile generation, profile repeatability, flow rate measurement, and lid-driven flow production. Finally, a microfluidic phantom for diffusion-weighted magnetic resonance imaging was developed for validation studies of long-distance cortical white matter connections. The diffusion phantom provides a reliable physical structure with which high resolution fiber tractography methods can be tested against. The diffusion phantom was fabricated using conventional photolithographic techniques with an internal channel network that mimics white matter fiber tracts and crossings. We show mapped tracts to the features inside of the phantom via post-processing of diffusion-weighted images

The development of sub-25 nm III-V High Electron Mobility Transistors

High Electron Mobility Transistors (HEMTs) are crucially important devices in microwave circuit applications. As the technology has matured, new applications have arisen, particularly at millimetre-wave and sub-millimetre wave frequencies. There now exists great demand for low-visibility, security and medical imaging in addition to telecommunications applications operating at frequencies well above 100 GHz. These new applications have driven demand for high frequency, low noise device operation; key areas in which HEMTs excel. As a consequence, there is growing incentive to explore the ultimate performance available from such devices. As with all FETs, the key to HEMT performance optimisation is the reduction of gate length, whilst optimally scaling the rest of the device and minimising parasitic extrinsic influences on device performance. Although HEMTs have been under development for many years, key performance metrics have latterly slowed in their evolution, largely due to the difficulty of fabricating devices at increasingly nanometric gate lengths and maintaining satisfactory scaling and device performance. At Glasgow, the world-leading 50 nm HEMT process developed in 2003 had not since been improved in the intervening five years. This work describes the fabrication of sub-25 nm HEMTs in a robust and repeatable manner by the use of advanced processing techniques: in particular, electron beam lithography and reactive ion etching. This thesis describes firstly the development of robust gate lithography for sub-25 nm patterning, and its incorporation into a complete device process flow. Secondly, processes and techniques for the optimisation of the complete device are described. This work has led to the successful fabrication of functional 22 nm HEMTs and the development of 10 nm scale gate pattern transfer: simultaneously some of the shortest gate length devices reported and amongst the smallest scale structures ever lithographically defined on III-V substrates. The first successful fabrication of implant-isolated planar high-indium HEMTs is also reported amongst other novel secondary processes

Statistical Yield Analysis and Design for Nanometer VLSI

Process variability is the pivotal factor impacting the design of high yield integrated circuits and systems in deep sub-micron CMOS technologies. The electrical and physical properties of transistors and interconnects, the building blocks of integrated circuits, are prone to significant variations that directly impact the performance and power consumption of the fabricated devices, severely impacting the manufacturing yield. However, the large number of the transistors on a single chip adds even more challenges for the analysis of the variation effects, a critical task in diagnosing the cause of failure and designing for yield. Reliable and efficient statistical analysis methodologies in various design phases are key to predict the yield before entering such an expensive fabrication process. In this thesis, the impacts of process variations are examined at three different levels: device, circuit, and micro-architecture. The variation models are provided for each level of abstraction, and new methodologies are proposed for efficient statistical analysis and design under variation. At the circuit level, the variability analysis of three crucial sub-blocks of today's system-on-chips, namely, digital circuits, memory cells, and analog blocks, are targeted. The accurate and efficient yield analysis of circuits is recognized as an extremely challenging task within the electronic design automation community. The large scale of the digital circuits, the extremely high yield requirement for memory cells, and the time-consuming analog circuit simulation are major concerns in the development of any statistical analysis technique. In this thesis, several sampling-based methods have been proposed for these three types of circuits to significantly improve the run-time of the traditional Monte Carlo method, without compromising accuracy. The proposed sampling-based yield analysis methods benefit from the very appealing feature of the MC method, that is, the capability to consider any complex circuit model. However, through the use and engineering of advanced variance reduction and sampling methods, ultra-fast yield estimation solutions are provided for different types of VLSI circuits. Such methods include control variate, importance sampling, correlation-controlled Latin Hypercube Sampling, and Quasi Monte Carlo. At the device level, a methodology is proposed which introduces a variation-aware design perspective for designing MOS devices in aggressively scaled geometries. The method introduces a yield measure at the device level which targets the saturation and leakage currents of an MOS transistor. A statistical method is developed to optimize the advanced doping profiles and geometry features of a device for achieving a maximum device-level yield. Finally, a statistical thermal analysis framework is proposed. It accounts for the process and thermal variations simultaneously, at the micro-architectural level. The analyzer is developed, based on the fact that the process variations lead to uncertain leakage power sources, so that the thermal profile, itself, would have a probabilistic nature. Therefore, by a co-process-thermal-leakage analysis, a more reliable full-chip statistical leakage power yield is calculated

Study, optimization and silicon implementation of a smart high-voltage conditioning circuit for electrostatic vibration energy harvesting system

La récupération de l'énergie des vibrations est un concept relativement nouveau qui peut être utilisé dans l'alimentation des dispositifs embarqués de puissance à micro-échelle avec l'énergie des vibrations omniprésentes dans l environnement. Cette thèse contribue à une étude générale des récupérateurs de l'énergie des vibrations (REV) employant des transducteurs électrostatiques. Un REV électrostatique typique se compose d'un transducteur capacitif, de l'électronique de conditionnement et d un élément de stockage. Ce travail se concentre sur l'examen du circuit de conditionnement auto-synchrone proposé en 2006 par le MIT, qui combine la pompe de charge à base de diodes et le convertisseur DC-DC inductif de type de flyback qui est entraîné par le commutateur. Cette architecture est très prometteuse car elle élimine la commande de grille précise des transistors utilisés dans les architectures synchrones, tandis qu'un commutateur unique se met en marche rarement. Cette thèse propose une analyse théorique du circuit de conditionnement. Nous avons développé un algorithme qui par commutation appropriée de flyback implémente la stratégie de conversion d'énergie optimale en tenant compte des pertes liées à la commutation. En ajoutant une fonction de calibration, le système devient adaptatif pour les fluctuations de l'environnement. Cette étude a été validée par la modélisation comportementale.Une autre contribution consiste en la réalisation de l'algorithme proposé au niveau du circuit CMOS. Les difficultés majeures de conception étaient liées à l'exigence de haute tension et à la priorité de la conception faible puissance. Nous avons conçu un contrôleur du commutateur haute tension de faible puissance en utilisant la technologie AMS035HV. Sa consommation varie entre quelques centaines de nanowatts et quelques microwatts, en fonction de nombreux facteurs - paramètres de vibrations externes, niveaux de tension de la pompe de charge, la fréquence de la commutation de commutateur, la fréquence de la fonction de calibration, etc.Nous avons également réalisé en silicium, fabriqué et testé un commutateur à haute tension avec une nouvelle architecture de l'élévateur de tension de faible puissance. En montant sur des composants discrets de la pompe de charge et du circuit de retour et en utilisant l'interrupteur conçu, nous avons caractérisé le fonctionnement large bande haute-tension du prototype de transducteur MEMS fabriqué à côté de cette thèse à l'ESIEE Paris. Lorsque le capteur est excité par des vibrations stochastiques ayant un niveau d'accélération de 0,8 g rms distribué dans la bande 110-170 Hz, jusqu'à 0,75 W de la puissance nette a été récupérée.Vibration energy harvesting is a relatively new concept that can be used in powering micro-scale power embedded devices with the energy of vibrations omnipresent in the surrounding. This thesis contributes to a general study of vibration energy harvesters (VEHs) employing electrostatic transducers. A typical electrostatic VEH consists of a capacitive transducer, conditioning electronics and a storage element. This work is focused on investigations of the reported by MIT in 2006 auto-synchronous conditioning circuit, which combines the diode-based charge pump and the inductive flyback energy return driven by the switch. This architecture is very promising since it eliminates precise gate control of transistors employed in synchronous architectures, while a unique switch turns on rarely. This thesis addresses the theoretical analysis of the conditioning circuit. We developed an algorithm that by proper switching of the flyback allows the optimal energy conversion strategy taking into account the losses associated with the switching. By adding the calibration function, the system became adaptive to the fluctuations in the environment. This study was validated by the behavioral modeling. Another contribution consists in realization of the proposed algorithm on the circuit level. The major design difficulties were related to the high-voltage requirement and the low-power design priority. We designed a high-voltage analog controller of the switch using AMS035HV technology. Its power consumption varies between several hundred nanowatts and a few microwatts, depending on numerous factors - parameters of external vibrations, voltage levels of the charge pump, frequency of the flyback switching, frequency of calibration function, etc. We also implemented on silicon, fabricated and tested a high-voltage switch with a novel low power level-shifting driver. By mounting on discrete components the charge pump and flyback circuit and employing the proposed switch, we characterized the wideband high-voltage operation of the MEMS transducer prototype fabricated alongside this thesis in ESIEE Paris. When excited with stochastic vibrations having an acceleration level of 0.8 g rms distributed in the band 110-170 Hz, up to 0.75 $\mu$W of net electrical power has been harvested.PARIS-JUSSIEU-Bib.électronique (751059901) / SudocSudocFranceF

Power-Scavenging MEMS Robots

This thesis includes the design, modeling, and testing of novel, power-scavenging, biologically inspired MEMS microrobots. Over one hundred 500-μm and 990-μm microrobots with two, four, and eight wings were designed, fabricated, characterized. These microrobots constitute the smallest documented attempt at powered flight. Each microrobot wing is comprised of downward-deflecting, laser-powered thermal actuators made of gold and polysilicon; the microrobots were fabricated in PolyMUMPs® (Polysilicon Multi-User MEMS Processes). Characterization results of the microrobots illustrate how wing-tip deflection can be maximized by optimizing the gold-topolysilicon ratio as well as the dimensions of the actuator-wings. From these results, an optimum actuator-wing configuration was identified. It also was determined that the actuator-wing configuration with maximum deflection and surface area yet minimum mass had the greatest lift-to-weight ratio. Powered testing results showed that the microrobots successfully scavenged power from a remote 660-nm laser. These microrobots also demonstrated rapid downward flapping, but none achieved flight. The results show that the microrobots were too heavy and lacked sufficient wing surface area. It was determined that a successfully flying microrobot can be achieved by adding a robust, light-weight material to the optimum actuator-wing configuration—similar to insect wings. The ultimate objective of the flying microrobot project is an autonomous, fully maneuverable flying microrobot that is capable of sensing and acting upon a target. Such a microrobot would be capable of precise lethality, accurate battle-damage assessment, and successful penetration of otherwise inaccessible targets