New Fault Tolerant Multicast Routing Techniques to Enhance Distributed-Memory Systems Performance

Distributed-memory systems are a key to achieve high performance computing and the most favorable architectures used in advanced research problems. Mesh connected multicomputer are one of the most popular architectures that have been implemented in many distributed-memory systems. These systems must support communication operations efficiently to achieve good performance. The wormhole switching technique has been widely used in design of distributed-memory systems in which the packet is divided into small flits. Also, the multicast communication has been widely used in distributed-memory systems which is one source node sends the same message to several destination nodes. Fault tolerance refers to the ability of the system to operate correctly in the presence of faults. Development of fault tolerant multicast routing algorithms in 2D mesh networks is an important issue. This dissertation presents, new fault tolerant multicast routing algorithms for distributed-memory systems performance using wormhole routed 2D mesh. These algorithms are described for fault tolerant routing in 2D mesh networks, but it can also be extended to other topologies. These algorithms are a combination of a unicast-based multicast algorithm and tree-based multicast algorithms. These algorithms works effectively for the most commonly encountered faults in mesh networks, f-rings, f-chains and concave fault regions. It is shown that the proposed routing algorithms are effective even in the presence of a large number of fault regions and large size of fault region. These algorithms are proved to be deadlock-free. Also, the problem of fault regions overlap is solved. Four essential performance metrics in mesh networks will be considered and calculated; also these algorithms are a limited-global-information-based multicasting which is a compromise of local-information-based approach and global-information-based approach. Data mining is used to validate the results and to enlarge the sample. The proposed new multicast routing techniques are used to enhance the performance of distributed-memory systems. Simulation results are presented to demonstrate the efficiency of the proposed algorithms

Auto-routing algorithm for field-programmable photonic gate arrays

[EN] Programmable multipurpose photonic integrated circuits require software routines to make use of their flexible operation as desired. In this work, we propose and demonstrate the use of a modified tree-search algorithm to automatically determine the optimum optical path in a field-programmable photonic gate array (FPPGA), based on end-user specifications, circuit architecture and imperfections in the realized FPPGA arising, for example, from fabrication variations. In such a scenario, the proposed algorithm only requires the hardware topology and the location of the connections of the FPPGA defining the optical path to be programmed. The routine is able to optimize the path over multiple and competing objectives like the overall length, accumulated loss and power consumption. In addition, should any region of the circuit suffer from any potential damage that may affect the device performance, this algorithm is also able to provide basic self-healing and fault-tolerance capabilities by supplying alternative paths through the photonic arrangement.The authors acknowledge financial support by the ERC ADG-2016 UMWP-Chip ERC-2016- ADG-741415, the ERC PoC-2019 FPPAs ERC-2019-POC-859927, the Generalitat Valenciana Future MWP technologies and applications PROMETEO 2017/103 research excellency award, and the COST Action CA16220 EUIMWP, the Advanced Instrumentation for World Class Microwave Photonics Research IDIFEDER/2018/031 and the Infraestructura para caracterizacion de Chips Fotonicos EQC2018-004683-PLópez-Hernández, A.; Pérez-López, D.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Auto-routing algorithm for field-programmable photonic gate arrays. Optics Express. 28(1):737-752. https://doi.org/10.1364/oe.382753737752281Soref, R. (2006). The Past, Present, and Future of Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 12(6), 1678-1687. doi:10.1109/jstqe.2006.883151Streshinsky, M., Ding, R., Liu, Y., Novack, A., Galland, C., Lim, A. E.-J., … Hochberg, M. (2013). The Road to Affordable, Large-Scale Silicon Photonics. Optics and Photonics News, 24(9), 32. doi:10.1364/opn.24.9.000032Smit, M., Leijtens, X., Ambrosius, H., Bente, E., van der Tol, J., Smalbrugge, B., … van Veldhoven, R. (2014). An introduction to InP-based generic integration technology. Semiconductor Science and Technology, 29(8), 083001. doi:10.1088/0268-1242/29/8/083001Carroll, L., Lee, J.-S., Scarcella, C., Gradkowski, K., Duperron, M., Lu, H., … O’Brien, P. (2016). Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices. Applied Sciences, 6(12), 426. doi:10.3390/app6120426Pérez, D., Gasulla, I., & Capmany, J. (2018). Field-programmable photonic arrays. Optics Express, 26(21), 27265. doi:10.1364/oe.26.027265Pérez, D., Gasulla, I., Capmany, J., & Soref, R. A. (2016). Reconfigurable lattice mesh designs for programmable photonic processors. Optics Express, 24(11), 12093. doi:10.1364/oe.24.012093Zhuang, L., Roeloffzen, C. G. H., Hoekman, M., Boller, K.-J., & Lowery, A. J. (2015). Programmable photonic signal processor chip for radiofrequency applications. Optica, 2(10), 854. doi:10.1364/optica.2.000854Pérez, D., Gasulla, I., Crudgington, L., Thomson, D. J., Khokhar, A. Z., Li, K., … Capmany, J. (2017). Multipurpose silicon photonics signal processor core. Nature Communications, 8(1). doi:10.1038/s41467-017-00714-1Pérez, D., & Capmany, J. (2019). Scalable analysis for arbitrary photonic integrated waveguide meshes. Optica, 6(1), 19. doi:10.1364/optica.6.000019Dijkstra, E. W. (1959). A note on two problems in connexion with graphs. Numerische Mathematik, 1(1), 269-271. doi:10.1007/bf01386390McQuillan, J., Richer, I., & Rosen, E. (1980). The New Routing Algorithm for the ARPANET. IEEE Transactions on Communications, 28(5), 711-719. doi:10.1109/tcom.1980.109472

Routing on the Channel Dependency Graph:: A New Approach to Deadlock-Free, Destination-Based, High-Performance Routing for Lossless Interconnection Networks

In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables. Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions

Communication algorithms for isotropic tasks in hypercubes and wraparound meshes

Cover title.Includes bibliographical references (p. 29-30).Research supported by the NSF. NSF-ECS-8519058 Research supported by the ARO. DAAL03-86-K-0171by Emmanouel A. Varvarigos and Dimitri P. Bertsekas

Recursive cubes of rings as models for interconnection networks

We study recursive cubes of rings as models for interconnection networks. We first redefine each of them as a Cayley graph on the semidirect product of an elementary abelian group by a cyclic group in order to facilitate the study of them by using algebraic tools. We give an algorithm for computing shortest paths and the distance between any two vertices in recursive cubes of rings, and obtain the exact value of their diameters. We obtain sharp bounds on the Wiener index, vertex-forwarding index, edge-forwarding index and bisection width of recursive cubes of rings. The cube-connected cycles and cube-of-rings are special recursive cubes of rings, and hence all results obtained in the paper apply to these well-known networks