FPGA IMPLEMENTATION OF LOW COMPLEXITY LINEAR PERIODICALLY TIME VARYING FILTER

ABSTRACT This paper presents a low complexity architecture for a linear periodically time varying (LPTV) filter. This architecture is based on multi-input multi-output(MIMO) representation of LPTV filters. The input signal is divided into blocks and parallel processing is incorporated, there by considerably reducing the effective input sampling rate. A single multiplier can be shared for each linear time invariant (LTI) filter in the representation. Each LTI filter is realized in the transposed direct form filter using multiplier less multiplication structures based on Binary common bit patterns (BCS). The proposed structure is simulated, synthesized and implemented on Virtex v50efg256-7 Field Programmable Gate Array (FPGA). LPTV systems can be expressed as generalization of Linear time invariant (LTI) systems. If the input for a M-period LPTV system is delayed by M samples, output is also delayed by the same number of samples. An LPTV system with a period of '1' is nothing but an LTI syste