Sensing circuits for multiwire proportional chambers

Integrated sensing circuits were designed, fabricated, and packaged for use in determining the direction and fluence of ionizing radiation passing through a multiwire proportional chamber. CMOS on sapphire was selected because of its high speed and low power capabilities. The design of the proposed circuits is described and the results of computer simulations are presented. The fabrication processes for the CMOS on sapphire sensing circuits and hybrid substrates are outlined. Several design options are described and the cost implications of each discussed. To be most effective, each chip should handle not more than 32 inputs, and should be mounted on its own hybrid substrate

DRAM을 위한 오프셋 캔슬링 센스 앰플리파이어의 설계와 오프셋 캔슬링 방법에 관한 분석

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.This thesis reports the offset issues of the sense amplifiers for DRAM (dynamic random-access memory) due to scaling-down of the devices. An offset-canceled DRAM sense amplifier with coupling capacitors to store and cancel the offset arising from random variations of the threshold voltages of the amplifying transistors. Analytical calculations of the average and standard deviation of the decision threshold voltages, defined as the voltage in the cell capacitor that bifurcates into binary levels when activated, are performed on various DRAM sensing schemes and their comparison results are presented. Based on the analysis, the proposed sense amplifier scheme using coupling capacitors is shown to offer the least amount of variation in the decision threshold, thereby increasing the sensing margin of the overall DRAM design. The coupling capacitors not only compensate for the random offset of the sense amplifiers, but also mitigate the effect of the mismatch of the bitline capacitances in the open bit line scheme. Measurement on the experimental chip fabricated in 65nm CMOS process validates the analysis and confirms superior performance of the proposed DRAM sensing scheme. Furthermore, it presents a gate voltage controlling scheme to reduce the offset due to pro-cess variation and a crosstalk canceling scheme to compensate for the data-dependent offsets.이 논문은 장치의 축소로 인한 DRAM (동적 랜덤 액세스 메모리) 용 감지 증폭기 (sense amplifier)의 오프셋 문제를 보고하고 이에 대해 분석합니다. 증폭 트랜지스터의 임계 전압 (threshold voltage) 의 무작위 변화 (random variation)로 인해 발생하는 오프셋을 저장 및 보상하기위한 커플링 커패시터 (coupling capacitor)가 있는 오프셋 보상 DRAM 감지 증폭기를 제안합니다. 셀 커패시터의 전압으로 정의되는 결정 임계 전압의 평균 및 표준 편차에 대한 분석 및 계산이 다양한 DRAM 감지 증폭기 방식에서 수행되며 비교 결과가 제공됩니다. 분석에 따르면, 커플링 커패시터를 사용하는 제안 된 감지 증폭기 방식은 결정 임계 값의 변동을 최소화하여 전체 DRAM 설계의 감지 마진을 증가시키는 것으로 나타났습니다. 커플링 커패시터는 감지 증폭기의 랜덤 오프셋을 보상 할뿐만 아니라 개방형 비트 라인 (open-bitline) 방식에서 비트 라인 커패시턴스의 불일치 효과를 완화합니다. 65nm CMOS 공정으로 제작 된 실험용 칩에 대한 측정은 분석을 검증하고 제안 된 DRAM 감지 방식의 우수한 성능을 확인합니다. 또한 프로세스 변동으로 인한 오프셋을 줄이기위한 게이트 전압 제어 방식과 데이터 의존적 오프셋을 보상하기위한 크로스 토크(crosstalk) 제거 방식을 제안합니다.ABSTRACT I CONTENTS II LIST OF FIGURES VI LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUND ON DRAM SENSE AMPLIFIERS 5 2.1 OVERVIEW 5 2.2 BASICS OF DRAM SENSE AMPLIFIERS 6 2.2.1 SENSE AMPLIFIER AND CORE STRUCTURE 6 2.2.2 READ OPERATION 9 2.3 DESIGN CHALLENGES FOR SENSE AMPLIFIER 12 2.3.1 SCALING-DOWN ISSUE AND SENSING MARGIN 12 2.3.2 SENSING TIME AND LAYOUT 15 CHAPTER 3 OFFSET MODELING AND ANALYSIS 17 3.1 OVERVIEW 17 3.2 TYPES OF OFFSETS 18 3.2.1 PROCESS VARIATION 18 3.2.2 INTRINSIC OFFSET 19 3.2.3 DATA-DEPENDENT OFFSET 20 3.3 OFFSET MODELS 22 3.3.1 LATCH SENSING TRAJECTORY 23 3.3.2 METASTABLE POINT 26 3.3.3 SENSING OFFSET 28 3.3.4 DECISION THRESHOLD VOLTAGE AND SENSING MARGIN 30 CHAPTER 4 ANALYSIS ON OFFSET-CANCELING SENSE AMPLIFIERS 32 4.1 OVERVIEW 32 4.2 COMPARISON ANALYSIS 35 4.3 CONVENTIONAL SENSE AMPLIFIER 36 4.4 OFFSET MISMATCH CALIBRATION SENSE AMPLIFIER 37 4.4.1 BITLINE SEPARATION SCHEME 39 4.5 OFFSET-CANCELING SENSE AMPLIFIER 43 4.5.1 RELATIONSHIP BETWEEN OMC AND OC 46 4.5.2 PRE-SENSING 48 CHAPTER 5 CAPACITOR-COUPLED OFFSET-CANCELED SENSE AMPLIFIER 51 5.1 OVERVIEW 51 5.2 MATHEMATICAL ANALYSIS 53 5.3 MONTE-CARLO SIMULATION RESULTS 55 5.4 EXPERIMENTAL RESULTS 61 CHAPTER 6 GATE VOLTAGE CONTROL SCHEME FOR PROCESS VARIATIONS 65 6.1 OVERVIEW 65 6.2 ARCHITECTURE 67 6.2.1 DIFFERENTIAL AMPLIFIER 67 6.2.2 OPERATIONAL AMPLIFIER (OP-AMP) 68 6.2.3 REPLICA SENSE AMPLIFIER 68 6.2.4 PMOS INVERTER 69 6.2.5 LOW DROPOUT VOLTAGE REGULATOR 69 6.2.6 BIAS GENERATOR 69 6.2.7 SENSE AMPLIFIER 70 6.2.8 LOOK-UP TABLE (LUT) 70 6.3 EFFECT OF GATE VOLTAGE CONTROL SCHEME 73 6.3.1 BEHAVIORAL MODELING 73 6.3.2 SIMULATION RESULTS 77 CHAPTER 7 CROSSTALK CANCELING SCHEME FOR DATA-DEPENDENT OFFSET CANCELATION 78 7.1 OVERVIEW 78 7.2 CROSSTALK EFFECTS 80 7.3 CROSSTALK CANCELING SCHEME 82 7.3.1 IMPLEMENTATION 82 7.3.2 EFFECT OF THE CROSSTALK CANCELING SCHEME 84 7.3.3 SIMULATION RESULTS 86 CHAPTER 8 CONCLUSION 88 BIBLIOGRAPHY 90 초 록 92Docto

Impact of atomistic device variability on analogue circuit design

Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC

A 100nA cardiac sensing channel

An ultra low power cardiac sensing channel for pacemaker applications, designed in 0.6um HV CMOS technology.Agencia Nacional de Investigación e Innovació

A 100nA cardiac sensing channel

An ultra low power cardiac sensing channel for pacemaker applications, designed in 0.6um HV CMOS technology.Agencia Nacional de Investigación e Innovació

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Design of a Flexible High Temperature Sram with Reduced Design Time

The objective of this research is to design an SRAM that works for the temperature range 0�C to 275�C, with an emphasis on reduction in design time by segregating critical modules and characterizing them. This way of characterizing the critical modules has proven to be helpful in duplicating them multiple times to achieve the size of the memory required, and also to meet the performance requirements. A High temperature SRAM system consisting of two 32k-bit SRAMs (an on-chip SRAM and an off-chip SPI SRAM) was designed and fabricated in 0.5um SOS Peregrine process. The methodology of design time reduction was used for SPI SRAM which is a variant of on-chip SRAM. The fabricated SPI SRAM was tested across the operating temperature range and upto 275�C, and the performance parameters were measured. The measured performance parameters were found to be in accordance with/exceed the required performance.School of Electrical & Computer Engineerin

An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier

Comparators are one of the most fundamental building blocks in all electronic systems involving analog and digital information. A comparator’s performance, or the accuracy of its output, is determined by the comparator’s offset voltage, which includes random offset and systematic offset. To guarantee the overall performance of an entire electronic system, offset-trimming techniques are often necessary to reduce inaccuracy. This study analyzes the offset errors in a representative comparator structure and describes an auto-calibration technique to systematically and significantly reducing the offset. The auto-calibration technique involves trimming of the comparator input transistor pair. Various trimming-switch structures are considered and compared, such as constant-sized drain switch (CDS), constant-sized gate switch (CGS), constant-sized source switch (CSS), binary-weighted source switch (BSS), and constant size split-source switch (SSS). The comparator and the offset auto-calibration circuits are designed using the GlobalFoundry 0.13μm process. Then an offset trimming algorithm, which is written on MATLAB, is applied to these circuits. Afterwards, the results are collected and analyzed. A comparison of linearity and trimming range (TR) achieved with different trimming switch structures is performed to demonstrate advantages and disadvantages of each switch scheme. The results are also plotted in a histogram to show the normal distribution of each scheme. Finally, offset cancellation technique is implemented in an operational amplifier (Op Amp) circuit with further analysis and comparison to prove the methodology