DESIGN OF A GAAS DISTRIBUTED AMPLIFIER WITH LC TRAPS BASED BROADBAND LINEARIZATION

Increasing the linearity of power amplifiers has been an important area of research because its signal integrity influences the performance of the entire transreceiver system and there are strict regulatory requirements on them. Due to the nonlinear behaviour of power amplifiers, third order intermodulation products are generated close to the desired signals and cannot be removed by filters. Increasing linearity will help bring these distortion products closer to the noise floor. However, it is not an easy task to increase linearity without trading off output power. To maintain the same level of output power generated but with higher linearity, many techniques, each with its own pros and cons, have been implemented to linearize an amplifier. Techniques involving feedback are seriously limited in terms of modulation bandwidth whereas methods such as predistortion and feedforward are very difficult to implement. This project seeks to use a simple method of placing terminations directly to the distributed amplifier (DA), making it a device level linearization technique and can be used in addition to the other system level techniques mentioned earlier. To increase linearity over a broad bandwidth of 0.5 to 3.0 GHz, this work proposes using low impedance terminations (LC traps) at the envelope frequency to the input and output of several distributed amplifiers. This research is novel since this is the first time broadband improvement in linearity has been demonstrated using the LC trap method. Two design iterations were completed (first design iteration has four variants to test the output trap while the second design iteration has three variants to test the input trap). The low impedance terminations are implemented using inductor-capacitor networks that are external to the monolithic microwave integrated circuit (MMIC). Design and layout of the DAs were carried out using Agilent’s Advanced Design System (ADS). Results show that placing the traps at the output of the DA does not truly affect the linearity of the device at lower frequencies but provide an improvement of 1.6 dB and 3.4 dB to the third-order output intercept point (OIP3) at 2.5 GHz and 3.0 GHz, respectively. With traps at the input, measurement results at -5 dBm input power, viii 1.375 V base bias (61 mA total collector current) and 10 MHz two tone spacing show a broadband improvement throughout the band (0.5 GHz to 3.0 GHz) of 3.3 dB to 7.4 dB in OIP3. Furthermore, the OIP3 is increased to 19.2 dB above P1dB. Results show that the improvement in OIP3 comes without lowering gain, return loss or P1dB and without causing any stability problems

Design of analog predistorter

Abstract. In this thesis, two analog predistorter circuits are designed for linearizing the CMOS power amplifier in MIMO transceivers. The first circuit uses two parallel transistors as conventional derivative superposition, where derivatives of the transistor drain currents are biased to have opposite phases for 3rd-order distortion components. This results in the cancellation and thus providing a very linear 3rd-order response. The other design, using complementary derivative superposition topology, has p- and n-type transistors with a common drain self-biasing to achieve expansive power gain. This is used to improve the 1-dB compression point of the CMOS power amplifier. Simulation results of conventional derivative superposition circuit show over 25 dB improvement in distortion level, while still providing a fair amount of power gain. Implementation with a CMOS power amplifier shows a 2.6 dB improvement in 1 dB compression point. With the circuit having expansive characteristics, adjustable gain-expansion behaviour is achieved. With the implemented digital bias control, expansion between 2.5 dB and 4 dB is achieved, with gain variation between -2.4 dB and 1 dB. With a CMOS power amplifier, 3.5 dB improvement in 1 dB compression point is achieved, allowing the power amplifier to be used with greater efficiency. Both circuits are implemented using 22nm CMOS SOI technology and submitted to fabrication

High Linearity Millimeter Wave Power Amplifiers with Novel Linearizer Techniques

Millimeter-wave communications have experienced phenomenal growth in recent years when limited frequency spectrum is occupied by the ever-developing communication services. The power amplifier, as the key component in the transmitter/receiver module of communication systems, affects performance of the whole system directly and receives much attention. For minimized distortion and optimum system performance, the non-constant en- velope modulation schemes used in communication systems have challenging requirements on linearity. As linearity is related to communication quality directly, several linearization techniques, such as predistortion and feedforward, are applied to power amplifier design. Predistortion method has the advantages over other techniques in relatively simple struc- ture and reasonable linearity improvement. But current predistortion circuits have quite limited performance improvement and relatively large insertion loss, which indicate the need for further research. In most of millimeter-wave amplifier design, great effort has been spent on output power or gain, while linearity is often ignored. As almost all the predistortion circuits operate at the RF frequencies, the linearized millimeter-wave com- munication circuit is still relatively immature and very challenging. This project is dedicated to solve the linearity problem faced by millimeter-wave power amplifier in communication systems, which lacks of e®ective techniques in this field. Linearity improvement with the predistortion method will be the key issue in this project and some original ideas for predistortion circuit design will be applied to millimeter-wave amplifiers. In this thesis, several predistortion circuits with novel structure were proposed, which provide a new approach for linearity improvement for millimeter-wave power am- plifier. A millimeter-wave power ampli¯er for LMDS applications built on GaAs pHEMT technology was developed to a high engineering standard, which works as the test bench for linearization. Actual operation and parasitic elements at tens of gigahertz have been taken into consideration during the design. Firstly, two novel predistorter structures based on the amplifier were proposed, one is based on an amplifier with a fixed bias circuit and the other is based on an amplifier with a nonlinear signal dependant bias circuit. These novel structures can improve the linearity while improving other metrics simultaneously, which can effectively solve the problem of insertion loss faced by the conventional structures. Besides this, an original predistortion circuit design methodology derived from frequency to signal amplitude transformation was proposed. Based on this methodology, several transfer functions were proposed and related predistortion circuits were built to linearize the power amplifier. As this methodology is quite different from the traditional approach, it can improve the linearity signifficantly while other metrics are affected slightly and has a broad prospect for application

High Linearity Millimeter Wave Power Amplifiers with Novel Linearizer Techniques

Millimeter-wave communications have experienced phenomenal growth in recent years when limited frequency spectrum is occupied by the ever-developing communication services. The power amplifier, as the key component in the transmitter/receiver module of communication systems, affects performance of the whole system directly and receives much attention. For minimized distortion and optimum system performance, the non-constant en- velope modulation schemes used in communication systems have challenging requirements on linearity. As linearity is related to communication quality directly, several linearization techniques, such as predistortion and feedforward, are applied to power amplifier design. Predistortion method has the advantages over other techniques in relatively simple struc- ture and reasonable linearity improvement. But current predistortion circuits have quite limited performance improvement and relatively large insertion loss, which indicate the need for further research. In most of millimeter-wave amplifier design, great effort has been spent on output power or gain, while linearity is often ignored. As almost all the predistortion circuits operate at the RF frequencies, the linearized millimeter-wave com- munication circuit is still relatively immature and very challenging. This project is dedicated to solve the linearity problem faced by millimeter-wave power amplifier in communication systems, which lacks of e®ective techniques in this field. Linearity improvement with the predistortion method will be the key issue in this project and some original ideas for predistortion circuit design will be applied to millimeter-wave amplifiers. In this thesis, several predistortion circuits with novel structure were proposed, which provide a new approach for linearity improvement for millimeter-wave power am- plifier. A millimeter-wave power ampli¯er for LMDS applications built on GaAs pHEMT technology was developed to a high engineering standard, which works as the test bench for linearization. Actual operation and parasitic elements at tens of gigahertz have been taken into consideration during the design. Firstly, two novel predistorter structures based on the amplifier were proposed, one is based on an amplifier with a fixed bias circuit and the other is based on an amplifier with a nonlinear signal dependant bias circuit. These novel structures can improve the linearity while improving other metrics simultaneously, which can effectively solve the problem of insertion loss faced by the conventional structures. Besides this, an original predistortion circuit design methodology derived from frequency to signal amplitude transformation was proposed. Based on this methodology, several transfer functions were proposed and related predistortion circuits were built to linearize the power amplifier. As this methodology is quite different from the traditional approach, it can improve the linearity signifficantly while other metrics are affected slightly and has a broad prospect for application

Digital predistortion of RF amplifiers using baseband injection for mobile broadband communications

Radio frequency (RF) power amplifiers (PAs) represent the most challenging design parts of wireless transmitters. In order to be more energy efficient, PAs should operate in nonlinear region where they produce distortion that significantly degrades the quality of signal at transmitter’s output. With the aim of reducing this distortion and improve signal quality, digital predistortion (DPD) techniques are widely used. This work focuses on improving the performances of DPDs in modern, next-generation wireless transmitters. A new adaptive DPD based on an iterative injection approach is developed and experimentally verified using a 4G signal. The signal performances at transmitter output are notably improved, while the proposed DPD does not require large digital signal processing memory resources and computational complexity. Moreover, the injection-based DPD theory is extended to be applicable in concurrent dual-band wireless transmitters. A cross-modulation problem specific to concurrent dual-band transmitters is investigated in detail and novel DPD based on simultaneous injection of intermodulation and cross-modulation distortion products is proposed. In order to mitigate distortion compensation limit phenomena and memory effects in highly nonlinear RF PAs, this DPD is further extended and complete generalised DPD system for concurrent dual-band transmitters is developed. It is clearly proved in experiments that the proposed predistorter remarkably improves the in-band and out-of-band performances of both signals. Furthermore, it does not depend on frequency separation between frequency bands and has significantly lower complexity in comparison with previously reported concurrent dual-band DPDs

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

Joint compensation of I/Q impairments and PA nonlinearity in mobile broadband wireless transmitters

The main focus of this thesis is to develop and investigate a new possible solution for compensation of in-phase/quadrature-phase (I/Q) impairments and power amplifier (PA) nonlinearity in wireless transmitters using accurate, low complexity digital predistortion (DPD) technique. After analysing the distortion created by I/Q modulators and PAs together with nonlinear crosstalk effects in multi-branch multiple input multiple output (MIMO) wireless transmitters, a novel two-box model is proposed for eliminating those effects. The model is realised by implementing two phases which provide an optimisation of the identification of any system. Another improvement is the capability of higher performance of the system without increasing the computational complexity. Compared with conventional and recently proposed models, the approach developed in this thesis shows promising results in the linearisation of wireless transmitters. Furthermore, the two-box model is extended for concurrent dual-band wireless transmitters and it takes into account cross-modulation (CM) products. Besides, it uses independent processing blocks for both frequency bands and reduces the sampling rate requirements of converters (digital-to-analogue and analogue-to-digital). By using two phases for the implementation, the model enables a scaling down of the nonlinear order and the memory depth of the applied mathematical functions. This leads to a reduced computational complexity in comparison with recently developed models. The thesis provides experimental verification of the two-box model for multi-branch MIMO and concurrent dual-band wireless transmitters. Accordingly, the results ensure both the compensation of distortion and the performance evaluation of modern broadband wireless transmitters in terms of accuracy and complexity

Analysis and Design of CMOS Radio-Frequency Power Amplifiers

The continuous advancement of semiconductor technologies, especially CMOS technology, has enabled exponential growth of the wireless communication industry. This explosive growth in turn has completely changed people’s lives. The CMOS feature size scale down greatly benefits digital logic integrations, which result in more powerful, versatile, and economical digital signal processing. Further research and development has pushed analog, mixed-signal, and even radio-frequency (RF) circuit blocks to be implemented and integrated in CMOS. Future generations of wireless communication call for even further level of integration, and as of now, the only circuit block that is rarely integrated in CMOS along with other parts of the system is the power amplifier (PA). Due to the fact that the PA in a wireless communication system is the most power-hungry circuit block, the integration of RF PA in CMOS would potentially not only save the cost of the wireless communication system real estate, but also reduce power consumption since die-to-die connection loss can be eliminated. RF PA design involves handling large amounts of voltage and current at the radio frequencies, which in the present wireless communication standards are in the range of giga-hertz. Therefore, a good understanding of many aspects related to RF PA design is necessary. Theoretical analysis of the communication system, nonlinear effects of the PA, as well as the impedance matching network is systematically presented. The analysis of the nonlinear effects proposes a formal mathematical description of the multitone nonlinearity, and through its relationship with two-tone test, the proposed PA design methodology would greatly reduce the design time while improving the design accuracy. A thorough analysis of the available architecture and design techniques for efficiency and linearity enhancement of RF PA shows that despite tremendous amounts of research and development into this topic, the fundamental tradeoff between the two still limits the RF PA implementation largely within SiGe, GaAs, and InP technologies. A RF PA for Wideband Code-Division Multiple Access (WCDMA) application standard is proposed, designed, and implemented in CMOS that demonstrates the proposed segmentation technique that resolved the main tradeoff between power efficiency and linearity. The innovative architecture developed in this work is not limited to applications in the WCDMA communication protocol or the CMOS technology, although CMOS implementation would take advantage of the readily available digital resources

Analysis and Design of CMOS Radio-Frequency Power Amplifiers

The continuous advancement of semiconductor technologies, especially CMOS technology, has enabled exponential growth of the wireless communication industry. This explosive growth in turn has completely changed people’s lives. The CMOS feature size scale down greatly benefits digital logic integrations, which result in more powerful, versatile, and economical digital signal processing. Further research and development has pushed analog, mixed-signal, and even radio-frequency (RF) circuit blocks to be implemented and integrated in CMOS. Future generations of wireless communication call for even further level of integration, and as of now, the only circuit block that is rarely integrated in CMOS along with other parts of the system is the power amplifier (PA). Due to the fact that the PA in a wireless communication system is the most power-hungry circuit block, the integration of RF PA in CMOS would potentially not only save the cost of the wireless communication system real estate, but also reduce power consumption since die-to-die connection loss can be eliminated. RF PA design involves handling large amounts of voltage and current at the radio frequencies, which in the present wireless communication standards are in the range of giga-hertz. Therefore, a good understanding of many aspects related to RF PA design is necessary. Theoretical analysis of the communication system, nonlinear effects of the PA, as well as the impedance matching network is systematically presented. The analysis of the nonlinear effects proposes a formal mathematical description of the multitone nonlinearity, and through its relationship with two-tone test, the proposed PA design methodology would greatly reduce the design time while improving the design accuracy. A thorough analysis of the available architecture and design techniques for efficiency and linearity enhancement of RF PA shows that despite tremendous amounts of research and development into this topic, the fundamental tradeoff between the two still limits the RF PA implementation largely within SiGe, GaAs, and InP technologies. A RF PA for Wideband Code-Division Multiple Access (WCDMA) application standard is proposed, designed, and implemented in CMOS that demonstrates the proposed segmentation technique that resolved the main tradeoff between power efficiency and linearity. The innovative architecture developed in this work is not limited to applications in the WCDMA communication protocol or the CMOS technology, although CMOS implementation would take advantage of the readily available digital resources

Adaptive Feedforward Amplifier Design

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2005Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2005Bu çalışmada, özünde doğrusal olmayan bir güç kuvvetlendiricisi uyarlanır ileri besleme yöntemi kullanılarak doğrusal hale getirilmiştir. Temel ileri beslemeli bir kuvvetlendirici iki adet döngüye sahiptir ve iki adet kuvvetlendirici kullanır. Birinci döngünün çıkışında güç kuvvetlendiricisinin (asıl kuvvetlendirici) neden olduğu hata işareti (iç-modülasyon bozulması) elde edilir. İkinci döngüde ise elde edilen bu hata işareti kullanılarak kuvvetlendirici çıkışında oluşan bozulma işareti yok edilir ve böylece kuvvetlendirici doğrusallaştırılmış olur. İleri besleme duyarlılığı çok yüksek olan bir yöntemdir. Bu nedenle her iki döngüde de birer uyarlanır denetim devresi kullanmak gereklidir. Bu denetim devresi her iki döngüdeki alt ve üst yollar arasındaki genlik ve faz dengesini kontrol altında tutmak ve her zaman için dengede kalmasını sağlamak için kullanılır. Sayısal işaret işleme (DSP) tabanlı kontrol devresi en küçük karesel ortalama (LMS) algoritmasını kullanarak uyarlama katsayılarını hesaplamaktadır. Her iki döngüdeki genlik ve faz ayarı vektör modülatörleri kullanarak yapılmıştır. Sonuç olarak, 5.8GHz uyarlanır ileri beslemeli kuvvetlendiricinin benzetimi yapılmıştır ve benzetim sonucunda kuvvetlendiricinin iç-modülasyon performansının 25dB iyileştirildiği gözlenmiştir.In this study, an inherently nonlinear power amplifier is linearized by using feedforward technique. A fundamental feedforward amplifier has two loops and uses two amplifiers. Error signal (intermodulation distortion) caused by power amplifier (main amplifier) is obtained at the output of the first loop. In the second loop, distortion signal at the output of the amplifier is cancelled by using this obtained error signal and thus amplifier is linearized. Feedforward is a method, which has a very high sensitivity. Hence, it is necessary to use adaptive control circuit in each loop. This control circuit is used to check on amplitude and phase balances between upper and lower branches of both loops and to guarantee that these balances is always provided. Digital Signal Processing (DSP) based control circuit calculates adaptation coefficients by using Least Mean Square (LMS) algorithm. Gain and phase adjustment is done by using vector modulators in both loops. Consequently, a 5.8GHz adaptive feedforward amplifier is simulated and as a result of simulation, it is observed that intermodulation performance of amplifier is improved by 25dB.Yüksek LisansM.Sc