6 research outputs found

    Defragmenting the Module Layout of a Partially Reconfigurable Device

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    Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by propose an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a two-dimensional strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve two-dimensional defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances.Comment: 10 pages, 11 figures, 1 table, Latex, to appear in "Engineering of Reconfigurable Systems and Algorithms" as a "Distinguished Paper

    Task scheduling and placement for reconfigurable devices

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    Partially reconfigurable devices allow the execution of different tasks at the same time, removing tasks when they finish and inserting new tasks when they arrive. This dissertation investigates scheduling and placing real-time tasks (tasks with deadline) on reconfigurable devices. One basic scheduler is the First-Fit scheduler. By allowing the First-Fit scheduler to retry tasks while they can satisfy their deadlines, we found that its performance can be enhanced to be better than other schedulers. We also proposed a placement idea based on partitioning the reconfigurable area into regions of various widths, assigning a task to a region based on its width. This idea has a similar rejection rate to a First-Fit scheduler that retries placing tasks and performs better than the First-Fit that does not retry tasks. Also, this regions-based scheduling method has a better running time. Managing how the space will be shared among tasks is a problems of interest. The main function of the free-space manager is to maintain information about the free space (areas not used by active tasks) after any placement or deletion of a task. Speed and efficiency of the free-space data structure are important as well as its effect on scheduler performance. We introduce the use of maximal horizontal strips and maximal vertical strips to represent free space. This resulted in a faster free space manager compared to what has been used in the area. Most researchers in the area of scheduling on reconfigurable devices assumed a homogeneous FPGA with only CLBs in the reconfigurable area. Most reconfigurable devices offered in the market, however, are not homogeneous but heterogeneous with other components between CLBs. We studied the effect of heterogeneity on the performance of schedulers designed for a homogeneous structure. We found that current schedulers result in worse performance when applied to a heterogeneous structure, but by simple modifications, we can apply them to a heterogeneous structure and achieve good performance. Consequently, the approach of studying homogeneous FPGAs is a valid one, as the scheduling ideas discovered there do carry over to heterogeneous FPGAs

    Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments

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    Field-Programmable Gate Arrays (FPGAs) provide highly flexible platforms to implement sophisticated data processing for scientific space instruments. The dynamic partial reconfiguration (DPR) capability of FPGAs allows it to schedule HW tasks. While this feature adds another dimension of processing power that can be exploited without significantly increasing system complexity and power consumption, there are still several challenges for an efficient DPR use. State-of-the-art concepts concentrate either on resource-efficient implementations at design time or flexible HW task scheduling at runtime. In this paper we propose a balanced algorithm that considers both optimization goals and is well suited for resource-limited space applications

    Parallel and Distributed Computing

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    The 14 chapters presented in this book cover a wide variety of representative works ranging from hardware design to application development. Particularly, the topics that are addressed are programmable and reconfigurable devices and systems, dependability of GPUs (General Purpose Units), network topologies, cache coherence protocols, resource allocation, scheduling algorithms, peertopeer networks, largescale network simulation, and parallel routines and algorithms. In this way, the articles included in this book constitute an excellent reference for engineers and researchers who have particular interests in each of these topics in parallel and distributed computing

    Control plane routing in photonic networks

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    The work described in the thesis investigates the features of control plane functionality for routing wavelength paths to serve a set of sub-wavelength demands. The work takes account of routing problems only found in physical network layers, notably analogue transmission impairments. Much work exists on routing connections for dynamic Wavelength-Routed Optical Networks (WRON) and to demonstrate their advantages over static photonic networks. However, the question of how agile the WRON should be has not been addressed quantitatively. A categorization of switching speeds is extended, and compared with the reasons for requiring network agility. The increase of effective network capacity achieved with increased agility is quantified through new simulations. It is demonstrated that this benefit only occurs within a certain window of network fill; achievement of significant gain from a more-agile network may be prevented by the operator’s chosen tolerable blocking probability. The Wavelength Path Sharing (WPS) scheme uses semi-static wavelengths to form unidirectional photonic shared buses, reducing the need for photonic agility. Making WPS more practical, novel improved routing algorithms are proposed and evaluated for both execution time and performance, offering significant benefit in speed at modest cost in efficiency. Photonic viability is the question of whether a path that the control plane can configure will work with an acceptable bit error rate (BER) despite the physical transmission impairments encountered. It is shown that, although there is no single approach that is simple, quick to execute and generally applicable at this time, under stated conditions approximations may be made to achieve a general solution that will be fast enough to enable some applications of agility. The presented algorithms, analysis of optimal network agility and viability assessment approaches can be applied in the analysis and design of future photonic control planes and network architectures
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