8 research outputs found
Development of a fault tolerant MOS field effect power semiconductor switching transistor
This work describes the development of a semiconductor switch to replace an electromechanical
contactor as used within the electrical power distribution system of the More
Electric Aircraft (MEA; a project begun in the 1990‟s by the United States Air Force). The
MEA is safety critical and therefore requires highest reliability components and systems, but
subsequent to a short circuit load fault the electro-mechanical contactor switch often welds
shut. This risk is increased when using high discharge energy lithium ion dc batteries.
Predominately the semiconductor switch controls inductive loads and is required to safely
turn off current of up to 10 times the nominal level during sporadic load fault events. The
switch requires the lowest static loss (lowest on state resistance), but also the lowest
dynamic loss (losses due to the switching event). Presently, unipolar devices provide the
lowest dynamic loss, but bipolar devices provide the lowest static loss. One possible solution
is use of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the area of which
is sized to suit the fault current, but at relatively high cost in terms of silicon area. The
resultant area is typically achieved by several die connected in parallel, unfortunately, such a
solution suffers from current share imbalance and the potential of cascade die failure. The
use of a parallel combination of unipolar and bipolar device types (MOSFET and Insulated
Gate Bipolar Transistors, IGBTs) to form a hybrid appears to offer the potential to reduce
the silicon area, and static loss, whilst reducing the impact of the increased dynamic losses
of the IGBT. Unfortunately, this goal requires optimised gate timing of the resultant hybrid
which proves challenging if the load current is to be shared appropriately during fault
switching in order to prevent failure. Some form of single MOS (Metal Oxide
Semiconductor) gated integrated hybrid device with self biased bipolar injection is therefore
required to ensure highest reliability through a non latching design which offers lowest
losses under all conditions and achieves an even temperature distribution.
In this work the novel concept of the integrated hybrid device has been investigated
at a low Blocking Voltage (BV) rating of 100 V, using computer simulation. The three
terminal hybrid silicon DMOS (Double diffused Metal Oxide Semiconductor) device utilises
a novel merged Schottky p-type injector to provide self biased entry into a reduced static
loss bipolar state in the event of high fault current. The device achieves a specific on state
resistance, R(ON,SP) = 1.16 mΩcm2 in bipolar mode (with BV=84 V), that is below the silicon
limit line and requires half the area of a traditional unipolar MOSFET to conduct fault
current. During comparative standard unclamped inductive switching trials, the hybrid
device provides a self clamping action which enables increased inductive energy switching
(higher inductance and/or higher load current), relative to that achieved by either the
MOSFET or IGBT. The hybrid conducting in bipolar mode switches an inductive load off
much faster than that typically achieved by an IGBT (toff =20 ns, in comparison to typically
>10 μs for an IGBT). This results in a low turn off energy for the hybrid (1.26*10-4 J/cm2) as
compared to that of the IGBT (8.72*10-3 J/cm2). The hybrid dynamic performance is
enhanced by the action of the merged Schottky contact which, unlike the IGBT, acts to limit
the emitter base voltage (VEB) of the internal PNP Bipolar Junction Transistor, BJT (the
integral PNP BJT is otherwise a shared feature with the IGBT). The self biased bipolar
activation is achieved at a forward bias (VAK) =1.3 V at temperature (T)= 300 K. The device
is latch up free across the operational temperature range of T=233 K to 400 K. A viable
charge balanced structure to increase the BV rating to approximately 600 V is also proposed.
The resulting performance of the single gated, self biased, hybrid, utilising a novel
merged Schottky/P type injector, could lead to a new class of rugged MOS gated power
switching devices in silicon and potentially silicon carbide
Contributions to the design of power modules for electric and hybrid vehicles: trends, design aspects and simulation techniques
314 p.En la última década, la protección del medio ambiente y el uso alternativo de energÃas renovables están tomando mayor relevancia tanto en el ámbito social y polÃtico, como cientÃfico. El sector del transporte es uno de los principales causantes de los gases de efecto invernadero y la polución existente, contribuyendo con hasta el 27 % de las emisiones a nivel global. En este contexto desfavorable, la electrificación de los vehÃculos de carretera se convierte en un factor crucial. Para ello, la transición de la actual flota de vehÃculos de carretera debe ser progresiva forzando la investigación y desarrollo de nuevos conceptos a la hora de producir vehÃculos eléctricos (EV) y vehÃculos eléctricos hÃbridos (HEV) más eficientes, fiables, seguros y de menor coste. En consecuencia, para el desarrollo y mejora de los convertidores de potencia de los HEV/EV, este trabajo abarca los siguientes aspectos tecnológicos: - Arquitecturas de la etapa de conversión de potencia. Las principales topologÃas que pueden ser implementadas en el tren de potencia para HEV/EV son descritas y analizadas, teniendo en cuenta las alternativas que mejor se adaptan a los requisitos técnicos que demandan este tipo de aplicaciones. De dicha exposición se identifican los elementos constituyentes fundamentales de los convertidores de potencia que forman parte del tren de tracción para automoción.- Nuevos dispositivos semiconductores de potencia. Los nuevos objetivos y retos tecnológicos solo pueden lograrse mediante el uso de nuevos materiales. Los semiconductores Wide bandgap (WBG), especialmente los dispositivos electrónicos de potencia basados en nitruro de galio (GaN) y carburo de silicio (SiC), son las alternativas más prometedoras al silicio (Si) debido a las mejores prestaciones que poseen dichos materiales, lo que permite mejorar la conductividad térmica, aumentar las frecuencias de conmutación y reducir las pérdidas.- Análisis de técnicas de rutado, conexionado y ensamblado de módulos de potencia. Los módulos de potencia fabricados con dies en lugar de dispositivos discretos son la opción preferida por los fabricantes para lograr las especificaciones indicadas por la industria de la automoción. Teniendo en cuenta los estrictos requisitos de eficiencia, fiabilidad y coste es necesario revisar y plantear nuevos layouts de las etapas de conversión de potencia, asà como esquemas y técnicas de paralelización de los circuitos, centrándose en las tecnologÃas disponibles.Teniendo en cuenta dichos aspectos, la presente investigación evalúa las alternativas de semiconductores de potencia que pueden ser implementadas en aplicaciones HEV/EV, asà como su conexionado para la obtención de las densidades de potencia requeridas, centrándose en la técnica de paralelización de semiconductores. Debido a la falta de información tanto cientÃfica como comercial e industrial sobre dicha técnica, una de las principales contribuciones del presente trabajo ha sido la propuesta y verificación de una serie de criterios de diseño para el diseño de módulos de potencia. Finalmente, los resultados que se han extraÃdo de los circuitos de potencia propuestos demuestran la utilidad de dichos criterios de diseño, obteniendo circuitos con bajas impedancias parásitas y equilibrados eléctrica y térmicamente. A nivel industrial, el conocimiento expuesto en la presente tesis permite reducir los tiempos de diseño a la hora de obtener prototipos de ciertas garantÃas, permitiendo comenzar la fase de prototipado habiéndose realizado comprobaciones eléctricas y térmicas
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Diamond Schottky barrier diodes
Research on wide band gap semiconductors suitable for power electronic
devices has spread rapidly in the last decade. The remarkable results exhibited by
silicon carbide (SiC) Schottky batTier diodes (SBDs), commercially available since
2001, showed the potential of wide band gap semiconductors for replacing silicon (Si)
in the range of medium to high voltage applications, where high frequency operation
is required. With superior physical and electrical properties, diamond became a
potential competitor to SiC soon after Element Six reported in 2002 the successful
synthesis of single crystal plasma deposited diamond with high catTier mobility.
This thesis discusses the remarkable properties of diamond and introduces
several device structures suitable for power electronics. The calculation of several
figures of merit emphasize the advantages of diamond with respect to silicon and
other wide band gap semiconductors and clearly identifies the areas where its impact
would be most significant. Information regarding the first synthesis of diamond,
which took place back in 1954, together with data regarding the modern technological
process which leads nowadays to high-quality diamond crystals suitable for electronic
devices, are reviewed. Models regarding the incomplete ionization of atomic dopants
and the variation of catTier mobility with doping level and temperature have been
elaborated and included in numerical simulators.
The study introduces the novel diamond M-i-P Schottky diode, a version of
power Schottky diode which takes advantage of the extremely high intrinsic hole
mobility. The structure overcomes the drawback induced by the high activation
energies of acceptor dopants in diamond which yield poor hole concentration at room
temperature. The complex shape of the on-state characteristic exhibited by diamond
M-i-P Schottky structures is thoroughly investigated by means of experimental
results, numerical simulations and theoretical considerations.
The fabrication of a ramp oxide termination on a diamond device is for the
first time reported in this thesis. Both experimental and simulated results show the
potential of this termination structure, previously built on Si and SiC power devices.
A comprehensive comparison between the ramp oxide and two other versions of the
field plate termination concept, the single step and the three-step structures, has been
performed, considering aspects such as electrical performance, occupied area,
complexity of technological process and cost.
Based on experimental results presented in this study, together with
predictions made via simulations and theoretical models, it is concluded that diamond
M-i-P Schottky diodes have the ability to deliver significantly higher performance
compared to that of SiC SBDs if issues such as material defects, Schottky contact
formation and measurement of reliable ionization coefficients are carefully addressed
in the near future
Feature Papers in Electronic Materials Section
This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book
Modelling the cryogenic properties of germanium for emerging liquid hydrogen power applications
Ph. D. ThesisIn recent years, there has been an increase in research focused towards the reduction and/or
elimination of greenhouse emissions from applications used in everyday life. In addressing
this, liquid hydrogen has been highlighted as an attractive alternative fuel source for commercial
vehicles due to it’s lower weight, higher power density and zero greenhouse emissions in
comparison to petrol and diesel fuels. Incorporating such a fuel source however introduces
a cryogenic environment of 20 K affecting the power electronics used to deliver the power
from source to load.
Herein, the physical properties of semiconductors influencing the overall efficiency of
devices within an H-bridge circuit are considered. From this, germanium is hypothesised to
be the most suitable semiconductor for power devices at or near temperatures of 20 K.
Closed-loop models are developed for the carrier concentration, carrier mobility, carrier
velocity, for both electrons and holes as a function of doping concentration and temperature
with critical analysis of the range of suitability for each. Multiple models are also developed
for both carrier concentration and carrier mobility which offer a trade off depending on
whether one requires accuracy or simplicity in calculation.
A significant influence on the device characteristics of MOSFETs is that of the oxide/semiconductor
interface. For the first time, ZrO2 is fabricated directly on germanium substrates
through the thermal oxidation of zirconium on germanium. The interface state density of
these capacitors are comparable to literature values offering a much cheaper and simpler
fabrication method for high-κ dielectric formation on germanium substrates. The leakage current density of the ZrO2 MOS capacitors are low in comparison to reported values and
are shown to decrease with decreasing temperature.
With the physical models of both bulk and interfacial germanium, multiple PiN germanium
diodes are simulated using technology computer aided design (TCAD) that show the
potential for germanium power devices with breakdown voltages in excess of 800 V at room
temperature and 400 V at 20 K. Simulations of vertical power MOSFETs incorporating
a ZrO2 interlayer show great promise for low temperature power electronics at or near
20 K where other commercial devices experience significant resistive losses. With the work
conducted here, vertical power MOSFETs fabricated using germanium and ZrO2 open the
gateway for low voltage applications incorporating liquid hydrogen fuel cells.Engineering and Physical Sciences Research Counci
Miniaturized Transistors, Volume II
In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before
Architectures d'intégration mixte monolithique-hybride de cellules de commutation de puissance sur puces multi-pôles silicium et assemblages optimisés
Actuellement, le module de puissance (convertisseur de puissance) standard hybride 2D est la technologie de référence qui domine le marché de la moyenne et de la forte puissance. Ce dernier se présente sous la forme d'un boitier à multi-puces discrètes. Les puces à semi-conducteur sont reliées entre elles par des faisceaux de wire-bonding (câblage par fils) pour former des cellules de commutation. La technologie d'interconnexion wire-bonding présente une grande maturité technologique, et ses modes de défaillance sont bien connus aujourd'hui. Toutefois, cette technologie est un facteur limitant en termes de performances électrique et thermomécanique, d'intégrabilité tridimensionnelle et de productivité. Ces travaux de thèse ont pour objectif de proposer et d'étudier de nouvelles architectures de convertisseurs de puissance très intégrés. Comparée à la technologie hybride, dite de référence, les architectures proposées visent à un degré d'intégration plus poussé, avec un effort d'intégration partagé et conjoint au niveau semi-conducteur (intégration monolithique) et au niveau assemblage (intégration hybride). L'intégration monolithique consiste à intégrer les interrupteurs formant les cellules de commutation dans de nouvelles architectures de puces, passant ainsi de la notion de puce dipôle à celle de macro-puce multi-pôle. L'intégration hybride repose sur le développement de nouvelles technologies de report et d'assemblage de ces macro-puces. Pour valider les trois nouvelles architectures d'intégrations proposées, la démarche a consisté dans un premier temps à étudier et valider le fonctionnement des nouvelles puces par des simulations SentaurusTM TCAD. Ensuite, les puces multi-pôles ont été réalisées en s'appuyant sur la filière IGBT disponible dans la plateforme de micro-fabrication du LAAS-CNRS. Pour finir, les puces ont été reportées sur des cartes PCB, afin de réaliser des circuits de conversions prototypes. La maille de commutation très intégrée proposée présente une inductance parasite inférieure au nanohenry, ce qui est remarquable comparée à ce qui est présenté dans l'état de l'art (env. 20 nH).Currently, the standard 2D hybrid power module (power converter) is the reference technology for the medium and high power market. This hybrid power module is a discrete multi-chip case. The semi-conductor chips are interconnected by wire-bonding to form switching cells. The wire-bonding interconnection technology is a limiting factor in terms of electrical and thermomechanical performances, three-dimensional integrability and productivity. The aim of this thesis is to study new architectures of very integrated power converters. Compared to the so-called hybrid reference technology, the proposed architectures aim at a greater degree of integration, with an integration at both the semi-conductor level (monolithic integration) and the packaging level (hybrid integration). Monolithic integration consists in integrating switching cells into new multi-terminal macro-chip architectures. Hybrid integration consists in developing of new technologies to assemble these macro-chips. To validate the different proposed integration architectures, the first step was to study and validate the operating modes of the new chips by SentaurusTM TCAD simulations. Then, the multi-terminal chips were realized in the micro and nanotechnology platform of LAAS-CNRS laboratory. Finally, the chips were bonded on PCB substrates to realize power converter circuit prototypes. The highly integrated switching loop presents a stray inductance loop lower than one nanohenry, wich is an important improvement as compared to the values reported in literature (about 20 nH)
Caractérisation et modélisation électro-thermique distribuée d'une puce IGBT : Application aux effets du vieillissement de la métallisation d'émetteur
Power modules, organized around power chips (IGBT, MOSFET, diodes, …), are increasingly needed for transportations systems such a rail, aeronautics and automobile. In all these application, power devices reliability is still a critical point. This is particularly the case in the powertrain of hybrid or electric vehicle in which power chips are often subjected to very high electrical and thermal stress levels such as hybrid or electric vehicle, power devices are subjected to very high electrical, thermal and mechanical stress levels which may affect their reliability.Thus, the ability to analyze the coupled phenomena and to accurately predict degradation mechanisms in power semiconductors and their effects due to electro-thermal and thermo-mechanical stress is essential. Especially on the semiconductor chip where significant physical interactions occur and its immediate vicinity. The aim of this work is to highlight the electro-mechanical and thermal stress and their effects on the semiconductor chip and its immediate vicinity, by evaluating the effects of damage using distributed models. This work consists of two parts :An original experimental approach concerning the elctro-thermal characterization of cross section power chips (IGBT and diodes). In this approach, it is exposed for the first time, an original way to characterize vertical thermal distributions inside high power silicon devices under forward bias. Thus, the vertical mapping of temperature and mechanical stress of IGBT and diode chip are presented. The impact of this work that is opens a wide field of investigations in high power semiconductor devices. The second part is theoretical and aims to implementing a distributed electro-thermal model of IGBT chip.The modeling strategy consists on a discretization of the power semiconductor chip in macro-cells with a distributed electro-thermal behavior over the chip area. In case of the IGBT devices each macro-cell is governed by the Hefner model and electrically linked by their terminals. Temperature variable used in these macro-cells are obtained by a nodal 3D-RC thermal model. This allows the distributed electro-thermal problem to be solved homogeneously and simultaneously by a circuit solver such as Simplorer. The aim of this model is to allow the accurate analysis of some effects ine the electrical and thermal coupling over the chip. Especially, this model should allow explaining some effects such as the contacts position over the die metallization and the ageing of the emitter metallization of the chip. In a first step, the model is used to clarify how the current and the temperature map are distributed over the chip according to the relative positions between cells and wire bond contacts on the top-metal during short-circuit operation. In a second step, we will show how dynamic latch-up failures may occur when trying to turn-off a short circuit process.Les convertisseurs de puissance structurés autour de puces de puissance (IGBT, MOSFET, diodes, ...) sont de plus en plus sollicités dans les systèmes de transport, du ferroviaire à l'aéronautique, en passant par l'automobile. Dans toutes ces applications, la fiabilité des composants constitue encore un point critique. C'est notamment le cas dans la chaîne de traction de véhicules électriques (VE) et hybrides (VH, où les puces sont souvent exposées à de fortes contraintes électriques, thermiques et mécaniques pouvant conduire à la défaillance. Dans ce contexte, l'amélioration des connaissances sur les effets des dégradations des composants semi-conducteurs de puissance et leurs assemblages dus au stress électrothermiques et thermomécaniques est incontournable. En particulier sur la puce semi-conductrice elle-même, siège d'interactions physiques importantes, et en son voisinage immédiat. Les objectifs de la thèse sont de mettre en lumière les stress électro-thermiques et mécaniques dans les puces et leurs effets sur la puce et son voisinage immédiat et à évaluer les effets de dégradations à l'aide de modèles distribués. Les travaux comportent ainsi deux volets. Un volet expérimental original visant la caractérisation électrothermique de puce de puissance (IGBT et diode) sur la base de micro-sections. La piste suivie par cette approche devrait permettre de rendre possible la caractérisation d'un certain nombre de grandeurs physiques (thermiques, électriques et mécaniques) sur les tranches sectionnées des puces sous polarisation (en statique, voire en dynamique) et ainsi contribuer à l'amélioration des connaissances de leur comportement. Ainsi, des cartographies de distributions verticales de température de puce IGBT et diode et de contraintes mécaniques sont présentées. C'est à notre connaissance une voie originale qui devrait permettre de d’ouvrir un large champ d'investigation dans le domaine de la puissance.Le second volet est théorique et consiste à mettre en place un modèle électrothermique distribué de puce IGBT. Cette modélisation comme nous l'envisageons implique de coupler dans un unique environnement (Simplorer) une composante thermique et une composant électrique. Le développement choisi passe par l'utilisation de modèle physique d'IGBT tels que celui de Hefner. Ce modèle est ensuite appliqué pour étudier le rôle et les effets du vieillissement de la métallisation de puce lors de régimes électriques extrêmes répétitifs tels que les courts-circuits. Un aspect original du travail est la démonstration par analyse numérique du mode de défaillance par latch-up dynamique à l'instant de la commande d'ouverture du courant de court-circuit. Ce phénomène bien qu'ayant été observé lors de vieillissement d'IGBT par répétition de courts-circuits n'avait à notre connaissance pas encore été simulé. La modélisation distribuée de la puce et la simulation du phénomène nous a ainsi permis de vérifier certaines hypothèses