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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices
Register-transfer-level power profiling for system-on-chip power distribution network design and signoff
Abstract. This thesis is a study of how register-transfer-level (RTL) power profiling can help the design and signoff of power distribution network in digital integrated circuits. RTL power profiling is a method which collects RTL power estimation results to a single power profile which then can be analysed in order to find interesting time windows for specifying power distribution network design and signoff.
The thesis starts with theory part. Complementary metal-oxide semiconductor (CMOS) inverter power dissipation is studied at first. Next, power distribution network structure and voltage drop problems are introduced. Voltage drop is demonstrated by using power distribution network impedance figures. Common on-chip power distribution network structure is introduced, and power distribution network design flow is outlined. Finally, decoupling capacitors function and impact on power distribution network impedance are thoroughly explained.
The practical part of the thesis contains RTL power profiling flow details and power profiling flow results for one simulation case in one design block. Also, some methods of improving RTL power estimation accuracy are discussed and calibration with extracted parasitic is then used to get new set of power profiling time windows. After the results are presented, overall RTL power estimation accuracy is analysed and resulted time windows are compared to reference gate-level time windows. RTL power profiling result analysis shows that resulted time windows match the theory and RTL power profiling seems to be a promising method for finding time windows for power distribution network design and signoff.Rekisterisiirtotason tehoprofilointi järjestelmäpiirin tehonsiirtoverkon suunnittelussa ja verifioinnissa. Tiivistelmä. Tässä työssä tutkitaan, miten rekisterisiirtotason (RTL) tehoprofilointi voi auttaa digitaalisten integroitujen piirien tehonsiirtoverkon suunnittelussa ja verifioinnissa. RTL-tehoprofilointi on menetelmä, joka analysoi RTL-tehoestimoinnista saadusta tehokäyrästä hyödyllisiä aikaikkunoita tehonsiirtoverkon suunnitteluun ja verifiointiin.
Työ alkaa teoriaosuudella, jonka aluksi selitetään, miten CMOS-invertteri kuluttaa tehoa. Seuravaksi esitellään tehonsiirtoverkon rakenne ja pahimmat tehonsiirtoverkon jännitehäviön aiheuttajat. Jännitehäviötä havainnollistetaan myös piirikaavioiden ja impedanssikäyrien avustuksella. Lisäksi integroidun piirin tehonsiirtoverkon suunnitteluvuo ja yleisin rakenne on esitelty. Lopuksi teoriaosuus käsittelee yksityiskohtaisesti ohituskondensaattoreiden toiminnan ja vaikutuksen tehonsiirtoverkon kokonaisimpedanssiin.
Työn kokeellisessa osuudessa esitellään ensin tehoprofiloinnin vuo ja sen jälkeen vuon tulokset yhdelle esimerkkilohkolle yhdessä simulaatioajossa. Lisäksi tässä osiossa käsitellään RTL-tehoestimoinnin tarkkuutta ja tehdään RTL-tehoprofilointi loisimpedansseilla kalibroidulle RTL-mallille. Lopuksi RTL-tehoestimoinnin tuloksia ja saatuja RTL-tehoprofiloinnin aikaikkunoita analysoidaan ja verrataan porttitason mallin tuloksiin. RTL-tehoprofiloinnin tulosten analysointi osoittaa, että saatavat aikaikkunat vastaavat teoriaa ja että RTL-tehoprofilointi näyttää lupaavalta menetelmältä tehosiirtoverkon analysoinnin ja verifioinnin aikaikkunoiden löytämiseen
Power supply noise coupling in a standard voltage reference circuit
Power supply noise coupling represents a challenge in the design of current and future analog and mixed-signal circuits and systems. In this thesis, power supply noise coupling is analyzed at the circuit level. As a representative study, power supply noise coupling in a voltage reference is studied. The precision of a voltage reference circuit is critical to the performance of other analog and RF circuits. Therefore, there is much value in developing a deeper understanding of the mechanisms through which power supply noise coupling occurs in this fundamental analog and RF system building block. A model representing the amount of noise coupling in the frequency domain is developed and verified through circuit simulations. A practical design solution for increasing high frequency power supply noise rejection is identified and evaluated. Finally, the effect of technology scaling on power supply noise is studied in two successive CMOS processes
On-Chip Digital Decoupling Capacitance Methodology
Signal integrity has become a major problem in digital IC design. One cause of this problem is device scaling which results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. Reductions in feature size also result in increased clock speeds leading to many different high frequency noise producing components. As on-chip area increases to allow for more computational capability, so does the amount of digital logic to be placed, magnifying the effects of noisy interconnect structures.
Supply noise, modeled as AV = Ldi/dt , is caused by rapid current spikes during a rise or fall time. Decoupling capacitors often fill empty on-chip space for the purpose of limiting this noise. This work introduces a novel methodology that attempts to quantify and locate decoupling capacitors within a power distribution network. The bondwire attached on the periphery of the face of the die is taken to be the dominant source of inductance. It is shown that distributing capacitance closer to the switching elements is most effective at reducing supply noise.
A chip has been designed using TSMC 90 nm technology that implements the ideas presented in this work. Simulation results show that noise fluctuations are high enough such that random placement of decoupling capacitance is not effective for large digital structures. The amount of interconnect generated on-chip noise increases with area, resulting in the need for an optimal decoupling scheme. As scaling continues, supply voltages and noise margins will decrease, creating the need for a robust decoupling capacitance methodology
3D ICs: An Opportunity for Fully-Integrated, Dense and Efficient Power Supplies
International audienceWith 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm 2 silicon area. An additional high density capacitance layer (100nF/mm 2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies
Allocating decoupling capacitors to reduce simultaneous switching noise on chips
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (leaves 108-110).L dI/dt noise due to simultaneous switching of circuits on chips is a growing problem in VLSI design. This kind of noise can lead to timing errors and significant circuit slowdowns, if not kept within reasonable bounds. The most common way of reducing this form of noise is the addition of decoupling capacitance on chip. However, adding decoupling capacitance can take significant area and can make routing very difficult. The goals of this thesis are twofold: first, to characterize the relationship between noise propagation on chip and parameters such as on-chip resistance and capacitance; and second, to develop an algorithm which will minimize the number of decoupling capacitors on chip while simultaneously reducing the noise to within acceptable boundaries.by Adam Granich Unikowsky.M.Eng
Design and Analysis of Power Distribution Networks in VLSI Circuits.
Rapidly switching currents of the on-chip devices can cause fluctuations in the supply voltage which can be classified as IR and Ldi/dt drops. The voltage fluctuations in a supply network can inject noise in a circuit which may lead to functional failures of the design. Power supply integrity verification is, therefore, a critical concern in high-performance designs. Also, with decreasing supply voltages, gate-delay is becoming increasingly sensitive to supply voltage variation. With ever-diminishing clock periods, accurate analysis of the impact of supply voltage on circuit performance has also become critical.
Increasing power consumption and clock frequency have exacerbated the Ldi/dt drop in every new technology generation. The Ldi/dt drop has become the dominant portion of the overall supply-drop in high performance designs. On-die passive decap, which has traditionally been used for suppressing Ldi/dt, has become expensive due to its area and leakage power overhead. This has created an urgent need for novel circuit techniques to suppress the Ldi/dt drop in power distribution networks.
We provide accurate algorithmic solutions for determining the worst-case supply-drop and the impact of supply noise on circuit performance. We propose a path-based and a block-based approach for computing the maximum circuit delay under power supply fluctuations. We also propose an early-mode supply-drop estimation approach and a statistical approach for power grid analysis. All the proposed approaches are vectorless and account for both IR and Ldi/dt drops. We also propose a performance-aware decoupling capacitance allocation technique which uses timing slacks to drive the optimization.
Finally, we present analog as well as all-digital circuit techniques for inductive supply noise suppression. The proposed all-digital circuit techniques were implemented in a test-chip, fabricated in a 0.13µm CMOS process. Measurements on the test-chip demonstrate a reduction in the supply fluctuations by 57% for a ramp loads and by 75% during resonance. We also present a low-power, all-digital on-chip oscilloscope for accurate measurement of supply noise. Supply noise measurements obtained from the on-chip oscilloscope were validated to conform well to those obtained from a traditional supply-drop monitor and direct on-chip probing.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58508/1/spant_1.pd
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