OFDM Coupled Compressive Sensing Algorithm for Stepped Frequency Ground Penetrating Radar

Dating back to as far as 1940, the US road and bridge infrastructure system has garnered quite the status for strategically connecting together half a continent. As monumental as the infrastructure\u27s status, is its rate of deterioration, with the average bridge age coming at a disconcerting 50 years. Aside from visual inspection, a battery of non-destructive tests were developed to conduct structural fault assessment and detect laminations, in order to preemptively take preventive measures. The mainstream commercially favored test is the impulse time domain ground penetrating radar (GPR). An extremely short, high voltage pulse is used to visualize cross-sections of the bridge decks. While effective and it does not disturb traffic flow, impulse radar suffers from major drawbacks. The drawbacks are namely, its limited dynamic range and high cost of system manufacturing. A less prominent yet highly effective system, stepped frequency continuous wave (SFCW) GPR, was developed to address the aforementioned drawbacks. Mostly developed for research centers and academia, SFCW boasts a high dynamic range and low cost of system manufacturing, while producing comparable if not identical results to the impulse counterpart. However, data procurement speed is an inherent problem in SFCW GPR, which seems to keep impulse radar in the lead for production and development. I am proposing a novel approach to elevate SFCW\u27s data acquisition speed and its scanning efficiency altogether. This approach combines an encoding method called orthogonal frequency division multiplexing (OFDM) and an emerging paradigm called compressive sensing (CS). In OFDM, a digital data stream, the transmit signal, is encoded on multiple carrier frequencies. These frequencies are combined in such a way to achieve orthogonality between the carrier frequencies, while mitigating any interference between said frequencies. In CS, a signal can be potentially reconstructed from a few samples below the standardized Nyquist rate. A novel design of the SFCW GPR architecture coupled with the OFDM-CS algorithm is proposed and evaluated using ideal channels and realistically modelled bridge decks

Impact of the nonlinear phenomenon on wireless radio telecommunications systems

Mestrado em Engenharia InformáticaA dimensão e heterogeneidade de recentes sistemas de telecomunicações sem fios impossibilitam a previsão do comportamento do sistema completo quando operado nos limites das suas capacidades. Isto torna irrealista o estudo do impacto do fenómeno não linear no desempenho dos sistemas em especial devido a que os resultados são diferentes quando estudados em separado ou embebidos num sistema. Este trabalho ultrapassa estas problemáticas através do uso de técnicas de co-simulação e de modelação do actual estado da arte as quais tornam possível uma representação mais realista do desempenho de um sistema. ABSTRACT: The dimension and heterogeneity of recent wireless radio telecommunication systems makes impracticable the prediction of the full system behavior when pushed to its performance limits. This makes unrealistic the study of the impact of the nonlinear phenomenon on the systems performance, especially because the results are different when studied alone or embedded in a system. This work overcomes these difficulties by using state-of-the-art cosimulation and modeling techniques that made possible the presentation of more realistic system performance evaluations

Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices

Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.Ph.D

Power and spectrally efficient integrated high-speed LED drivers for visible light communication

Recent trends in mobile broadband indicates that the available radio frequency (RF) spectrum will not be enough to support the data requirements of the immediate future. Visible light communication, which uses visible spectrum to transmit wirelessly could be a potential solution to the RF ’Spectrum Crunch’. Thus there is growing interest all over the world in this domain with support from both academia and industry. Visible light communication( VLC) systems make use of light emitting diodes (LEDs), which are semiconductor light sources to transmit information. A number of demonstrators at different data capacity and link distances has been reported in this area. One of the key problems holding this technology from taking off is the unavailability of power efficient, miniature LED drive schemes. Reported demonstrators, mostly using either off the shelf components or arbitrary waveform generators (AWGs) to drive the LEDs have only started to address this problem by adopting integrated drivers designed for driving lighting installations for communications. The voltage regulator based drive schemes provide high power efficiency (> 90 %) but it is difficult to realise the fast switching required to achieve the Mbps or Gbps data rates needed for modern wireless communication devices. In this work, we are exploiting CMOS technology to realise an integrated LED driver for VLC. Instead of using conventional drive schemes (digital to analogue converter (DAC) + power amplifier or voltage regulators), we realised a current steering DAC based LED driver operating at high currents and sampling rates whilst maintaining power efficiency. Compared to a commercial AWG or discrete LED driver, circuit realised utilisng complementary metal oxide semiconductor (CMOS) technology has resulted in area reduction (29mm2). We realised for the first time a multi-channel CMOS LED driver capable of operating up to a 500 MHz sample rate at an output current of 255 mA per channel and >70% power efficiency. We were able to demonstrate the flexibility of the driver by employing it to realise VLC links using micro LEDs and commercial LEDs. Data rates up to 1 Gbps were achieved using this system employing a multiple input, multiple output (MIMO) scheme. We also demonstrated the wavelength division multiplexing ability of the driver using a red/green/blue commercial LED. The first integrated digital to light converter (DLC), where depending on the input code, a proportional number of LEDs are turned ON, realising a data converter in the optical domain, is also an output from this research. In addition, we propose a differential optical drive scheme where two output branches of a current DAC are used to drive two LEDs achieving higher link performance and power efficiency compared to single LED drive

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures

Analysis and Design of CMOS Radio-Frequency Power Amplifiers

The continuous advancement of semiconductor technologies, especially CMOS technology, has enabled exponential growth of the wireless communication industry. This explosive growth in turn has completely changed people’s lives. The CMOS feature size scale down greatly benefits digital logic integrations, which result in more powerful, versatile, and economical digital signal processing. Further research and development has pushed analog, mixed-signal, and even radio-frequency (RF) circuit blocks to be implemented and integrated in CMOS. Future generations of wireless communication call for even further level of integration, and as of now, the only circuit block that is rarely integrated in CMOS along with other parts of the system is the power amplifier (PA). Due to the fact that the PA in a wireless communication system is the most power-hungry circuit block, the integration of RF PA in CMOS would potentially not only save the cost of the wireless communication system real estate, but also reduce power consumption since die-to-die connection loss can be eliminated. RF PA design involves handling large amounts of voltage and current at the radio frequencies, which in the present wireless communication standards are in the range of giga-hertz. Therefore, a good understanding of many aspects related to RF PA design is necessary. Theoretical analysis of the communication system, nonlinear effects of the PA, as well as the impedance matching network is systematically presented. The analysis of the nonlinear effects proposes a formal mathematical description of the multitone nonlinearity, and through its relationship with two-tone test, the proposed PA design methodology would greatly reduce the design time while improving the design accuracy. A thorough analysis of the available architecture and design techniques for efficiency and linearity enhancement of RF PA shows that despite tremendous amounts of research and development into this topic, the fundamental tradeoff between the two still limits the RF PA implementation largely within SiGe, GaAs, and InP technologies. A RF PA for Wideband Code-Division Multiple Access (WCDMA) application standard is proposed, designed, and implemented in CMOS that demonstrates the proposed segmentation technique that resolved the main tradeoff between power efficiency and linearity. The innovative architecture developed in this work is not limited to applications in the WCDMA communication protocol or the CMOS technology, although CMOS implementation would take advantage of the readily available digital resources

Analysis and Design of CMOS Radio-Frequency Power Amplifiers

The continuous advancement of semiconductor technologies, especially CMOS technology, has enabled exponential growth of the wireless communication industry. This explosive growth in turn has completely changed people’s lives. The CMOS feature size scale down greatly benefits digital logic integrations, which result in more powerful, versatile, and economical digital signal processing. Further research and development has pushed analog, mixed-signal, and even radio-frequency (RF) circuit blocks to be implemented and integrated in CMOS. Future generations of wireless communication call for even further level of integration, and as of now, the only circuit block that is rarely integrated in CMOS along with other parts of the system is the power amplifier (PA). Due to the fact that the PA in a wireless communication system is the most power-hungry circuit block, the integration of RF PA in CMOS would potentially not only save the cost of the wireless communication system real estate, but also reduce power consumption since die-to-die connection loss can be eliminated. RF PA design involves handling large amounts of voltage and current at the radio frequencies, which in the present wireless communication standards are in the range of giga-hertz. Therefore, a good understanding of many aspects related to RF PA design is necessary. Theoretical analysis of the communication system, nonlinear effects of the PA, as well as the impedance matching network is systematically presented. The analysis of the nonlinear effects proposes a formal mathematical description of the multitone nonlinearity, and through its relationship with two-tone test, the proposed PA design methodology would greatly reduce the design time while improving the design accuracy. A thorough analysis of the available architecture and design techniques for efficiency and linearity enhancement of RF PA shows that despite tremendous amounts of research and development into this topic, the fundamental tradeoff between the two still limits the RF PA implementation largely within SiGe, GaAs, and InP technologies. A RF PA for Wideband Code-Division Multiple Access (WCDMA) application standard is proposed, designed, and implemented in CMOS that demonstrates the proposed segmentation technique that resolved the main tradeoff between power efficiency and linearity. The innovative architecture developed in this work is not limited to applications in the WCDMA communication protocol or the CMOS technology, although CMOS implementation would take advantage of the readily available digital resources

Discrete Wavelet Transforms

The discrete wavelet transform (DWT) algorithms have a firm position in processing of signals in several areas of research and industry. As DWT provides both octave-scale frequency and spatial timing of the analyzed signal, it is constantly used to solve and treat more and more advanced problems. The present book: Discrete Wavelet Transforms: Algorithms and Applications reviews the recent progress in discrete wavelet transform algorithms and applications. The book covers a wide range of methods (e.g. lifting, shift invariance, multi-scale analysis) for constructing DWTs. The book chapters are organized into four major parts. Part I describes the progress in hardware implementations of the DWT algorithms. Applications include multitone modulation for ADSL and equalization techniques, a scalable architecture for FPGA-implementation, lifting based algorithm for VLSI implementation, comparison between DWT and FFT based OFDM and modified SPIHT codec. Part II addresses image processing algorithms such as multiresolution approach for edge detection, low bit rate image compression, low complexity implementation of CQF wavelets and compression of multi-component images. Part III focuses watermaking DWT algorithms. Finally, Part IV describes shift invariant DWTs, DC lossless property, DWT based analysis and estimation of colored noise and an application of the wavelet Galerkin method. The chapters of the present book consist of both tutorial and highly advanced material. Therefore, the book is intended to be a reference text for graduate students and researchers to obtain state-of-the-art knowledge on specific applications

Physical Layer Techniques for Wireless Communication Systems

The increasing diffusion of mobile devices requiring, everywhere and every time, reliable connections able to support the more common applications, induced in the last years the deployment of telecommunication networks based on technologies capable to respond effectively to the ever-increasing market demand, still a long way off from saturation level. Multicarrier transmission techniques employed in standards for local networks (Wi-Fi) and metropolitan networks (WiMAX) and for many years hot research topic, have been definitely adopted beginning from the fourth generation of cellular systems (LTE). The adoption of multicarrier signaling techniques if on one hand has brought significant advantages to counteract the detrimental effects in environments with particularly harsh propagation channel, on the other hand, has imposed very strict requirements on sensitivity to recovery errors of the carrier frequency offset (CFO) due to the resulting impact on correct signal detection. The main focus of the thesis falls in this area, investigating some aspects relating to synchronization procedures for system based on multicarrier signaling. Particular reference will be made to a network entry procedure for LTE networks and to CFO recovery for OFDM, fltered multitone modulation and direct conversion receivers. Other contributions pertaining to physical layer issues for communication systems, both radio and over acoustic carrier, conclude the thesis

An RF System Design for an Ultra Wideband Indoor Positioning System

Three main elements for an indoor positioning and navigation system design are the signal structure, the signal processing algorithm and the digital and RF prototype hardware. This thesis focuses on the design and development of RF prototype hardware. The signal structure being used in the precise positioning system discussed in this thesis is a Multicarrier-Ultra Wideband (MC-UWB) type signal structure. Unavailability of RF modules suitable for MC-UWB based systems, led to design and development of custom RF transmitter and receiver modules which can be used for extensive field testing. The lack of RF design guidelines for multicarrier positioning systems that operate over fractional bandwidth ranging from 10% to 25% makes the RF design challenging as the RF components are stressed using multicarrier signal in a way not anticipated by the designers. This thesis, first presents simulation based performance evaluation of impulse radio based and multicarrier based indoor positioning systems. This led to an important revelation that multicarrier based positioning system is preferred over impulse radio based positioning systems. Following this, ADS simulations for a direct upconversion transmitter and a direct downconversion receiver, using multicarrier signal structure is presented. The thesis will then discuss the design and performance of the 24% fractional bandwidth RF prototype transmitter and receiver custom modules. This optimized 24% fractional bandwidth RF design, under controlled testing environment demonstrates positioning accuracy improvement by 2-4 times over the initial 11% fractional bandwidth non-optimized RF design. The thesis will then present the results of various indoor wireless tests using the optimized RF prototype modules which led to better understanding of the issues in a field deployable indoor positioning system