A describing function study of saturated quantization and its application to the stability analysis of multi-bit sigma delta modulators

Just as their single-bit counterparts, multi-bit sigma delta modulators exhibit nonlinear behavior due to the presence of the quantizer in the loop. In the multi-bit case this is caused by the fact that any quantizer has a limited output range and hence gives an implicit saturation effect. Due to this, any multi-bit modulator is prone to modulator overloading. Unfortunately, until now, designers had to rely on extensive time-domain simulations to predict the overloading level, because there is no adequate analytical theory to model this effect. In this work, we have developed such an analytical theory based on multiple input describing function analysis. This way, we obtained expressions for the signal gain, the noise gain and the variance of the quantization noise. Here, both the case of DC as well as sinusoidal signals was considered. These results were used for the stability analysis of multi-bit Sigma Delta modulators, which allows to predict the overloading level. Code implementing the proposed expressions is available for download at http://cas1.elis.ugent. be/cas/en/download

Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

An RF Carrier Bursting System using Partial Quantization Noise Cancellation

This paper introduces a novel method for bandpass cancellation of the quantization noise occurring in high efficiency, envelope pulsed transmitter architectures - or carrier bursting. An equivalent complex baseband model of the proposed system, including the Sigma Delta-modulator and cancellation signal generation, is developed. Analysis of the baseband model is performed, leading to analytical expressions of the power amplifier drain efficiency, assuming the use of an ideal class B power amplifier. These expressions are further used to study the impact of key system parameters, i.e. the compensation signal variance and clipping probability, on the class~B power amplifier drain efficiency and signal-to-noise ratio. The paper concludes with simulations followed by practical measurements in order to validate the functionality of the method and to evaluate the performance-trend predictions made by the theoretical framework in terms of efficiency and spectral purity

1-Bit processing based model predictive control for fractionated satellite missions

In this thesis, a 1-bit processing based Model Predictive Control (OBMPC) structure is proposed for a fractionated satellite attitude control mission. Despite the appealing advantages of the MPC algorithm towards constrained MIMO control applications, implementing the MPC algorithm onboard a small satellite is certainly challenging due to the limited onboard resources. The proposed design is based on the 1-bit processing concept, which takes advantage of the affine relation between the 1-bit state feedback and multi-bit parameters to implement a multiplier free MPC controller. As multipliers are the major power consumer in online optimization, the OBMPC structure is proven to be more efficient in comparison to the conventional MPC implementation in term of power and circuit complexity. The system is in digital control nature, affected by quantization noise introduced by Δ∑ modulators. The stability issues and practical design criteria are also discussed in this work. Some other aspects are considered in this work to complete the control system. Firstly, the implementation of the OBMPC system relies on the 1-bit state feedbacks. Hence, 1-bit sensing components are needed to implement the OBMPC system. While the ∆∑ modulator based Microelectromechanical systems (MEMS) gyroscope is considered in this work, it is possible to implement this concept into other sensing components. Secondly, as the proposed attitude mission is based on the wireless inter-satellite link (ISL), a state estimator is required. However, conventional state estimators will once again introduce multi-bit signals, and compromise the simple, direct implementation of the OBMPC controller. Therefore, the 1-bit state estimator is also designed in this work to satisfy the requirements of the proposed fractionated attitude control mission. The simulation for the OBMPC is based on a 2U CubeSat model in a fractionated satellite structure, in which the payload and actuators are separated from the controller and controlled via the ISL. Matlab simulations and FPGA implementation based performance analysis shows that the OBMPC is feasible for fractionated satellite missions and is advantageous over the conventional MPC controllers

1-Bit processing based model predictive control for fractionated satellite missions

In this thesis, a 1-bit processing based Model Predictive Control (OBMPC) structure is proposed for a fractionated satellite attitude control mission. Despite the appealing advantages of the MPC algorithm towards constrained MIMO control applications, implementing the MPC algorithm onboard a small satellite is certainly challenging due to the limited onboard resources. The proposed design is based on the 1-bit processing concept, which takes advantage of the affine relation between the 1-bit state feedback and multi-bit parameters to implement a multiplier free MPC controller. As multipliers are the major power consumer in online optimization, the OBMPC structure is proven to be more efficient in comparison to the conventional MPC implementation in term of power and circuit complexity. The system is in digital control nature, affected by quantization noise introduced by Δ∑ modulators. The stability issues and practical design criteria are also discussed in this work. Some other aspects are considered in this work to complete the control system. Firstly, the implementation of the OBMPC system relies on the 1-bit state feedbacks. Hence, 1-bit sensing components are needed to implement the OBMPC system. While the ∆∑ modulator based Microelectromechanical systems (MEMS) gyroscope is considered in this work, it is possible to implement this concept into other sensing components. Secondly, as the proposed attitude mission is based on the wireless inter-satellite link (ISL), a state estimator is required. However, conventional state estimators will once again introduce multi-bit signals, and compromise the simple, direct implementation of the OBMPC controller. Therefore, the 1-bit state estimator is also designed in this work to satisfy the requirements of the proposed fractionated attitude control mission. The simulation for the OBMPC is based on a 2U CubeSat model in a fractionated satellite structure, in which the payload and actuators are separated from the controller and controlled via the ISL. Matlab simulations and FPGA implementation based performance analysis shows that the OBMPC is feasible for fractionated satellite missions and is advantageous over the conventional MPC controllers

Digital electronic predistortion for optical communications

The distortion of optical signals has long been an issue limiting the performance of communication systems. With the increase of transmission speeds the effects of distortion are becoming more prominent. Because of this, the use of methods known from digital signal processing (DSP) are being introduced to compensate for them. Applying DSP to improve optical signals has been limited by a discrepancy in digital signal processing speeds and optical transmission speeds. However high speed Field Programmable Gate Arrays (FPGA) which are sufficiently fast have now become available making DSP experiments without costly ASIC implementation possible for optical transmission experiments. This thesis focuses on Look Up Table (LUT) based digital Electronic Predistortion (EPD) for optical transmission. Because it is only one out of many possible implementations of EPD, it has to be placed in context with other EPD techniques and other distortion combating techniques in general, especially since it is possible to combine the different techniques. Building an actual transmitter means that compromises and decisions have to be made in the design and implementation of an EPD based system. These are based on balancing the desire to achieve optimal performance with technological and economic limitations. This is partly done using optical simulations to asses the performance. This thesis describes a novel experimental transmitter that has been built as part of this research applying LUT based EPD to an optical signal. The experimental transmitter consists of a digital design (using a hardware description language) for a pair of FPGAs and an analogue optical/electronic setup including two standard DAC integrated circuits. The DSP in the transmitter compensated for both chromatic dispersion and self phase modulation. We achieved transmission of 10.7 Gb/s non-return-to-zero (NRZ) signals with a +4 dBm launch power over 450 km keeping the required optical-signal-to-noise-ratio (OSNR) for a bit-error-rate of 2x10^{-3} below 11 dB. In doing so we showed experimentally, for the first time, that nonlinear effects can be compensated with this approach and that the combination of FPGA-DAC is a viable approach for an experimental setup