1,186 research outputs found

    On variable frequency microwave processing of heterogeneous chip-on-board assemblies

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    Variable Frequency Microwave (VFM) processing of heterogeneous chip-on-board assemblies is assessed using a multiphysics modelling approach. The Frequency Agile Microwave Oven Bonding System (FAMOBS) is capable of rapidly processing individual packages on a Chip-On-Board (COB) assembly. This enables each package to be processed in an optimal manner, with temperature ramp rate, maximum temperature and process duration tailored to the specific package, a significant benefit in assemblies containing disparate package types. Such heterogeneous assemblies may contain components such as large power modules alongside smaller modules containing low thermal budget materials with highly disparate processing requirements. The analysis of two disparate packages has been assessed numerically to determine the applicability of the dual section microwave system to curing heterogeneous devices and to determine the influence of differing processing requirements of optimal process parameters

    MODELING THE PHYSICS OF FAILURE FOR ELECTRONIC PACKAGING COMPONENTS SUBJECTED TO THERMAL AND MECHANICAL LOADING

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    This dissertation presents three separate studies that examined electronic components using numerical modeling approaches. The use of modeling techniques provided a deeper understanding of the physical phenomena that contribute to the formation of cracks inside ceramic capacitors, damage inside plated through holes, and to dynamic fracture of MEMS structures. The modeling yielded numerical substantiations for previously proposed theoretical explanations. Multi-Layer Ceramic Capacitors (MLCCs) mounted with stiffer lead-free solder have shown greater tolerance than tin-lead solder for single cycle board bending loads with low strain rates. In contrast, flexible terminations have greater tolerance than stiffer standard terminations under the same conditions. It has been proposed that residual stresses in the capacitor account for this disparity. These stresses have been attributed to the higher solidification temperature of lead free solders coupled with the CTE mismatch between the board and the capacitor ceramic. This research indicated that the higher solidification temperatures affected the residual stresses. Inaccuracies in predicting barrel failures of plated through holes are suspected to arise from neglecting the effects of the reflow process on the copper material. This research used thermo mechanical analysis (TMA) results to model the damage in the copper above the glass transition temperature (Tg) during reflow. Damage estimates from the hysteresis plots were used to improve failure predictions. Modeling was performed to examine the theory that brittle fracture in MEMS structures is not affected by strain rates. Numerical modeling was conducted to predict the probability of dynamic failure caused by shock loads. The models used a quasi-static global gravitational load to predict the probability of brittle fracture. The research presented in this dissertation explored drivers for failure mechanisms in flex cracking of capacitors, barrel failures in plated through holes, and dynamic fracture of MEMS. The studies used numerical modeling to provide new insights into underlying physical phenomena. In each case, theoretical explanations were examined where difficult geometries and complex material properties made it difficult or impossible to obtain direct measurements

    Fiabilité de l’underfill et estimation de la durée de vie d’assemblages microélectroniques

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    Abstract : In order to protect the interconnections in flip-chip packages, an underfill material layer is used to fill the volumes and provide mechanical support between the silicon chip and the substrate. Due to the chip corner geometry and the mismatch of coefficient of thermal expansion (CTE), the underfill suffers from a stress concentration at the chip corners when the temperature is lower than the curing temperature. This stress concentration leads to subsequent mechanical failures in flip-chip packages, such as chip-underfill interfacial delamination and underfill cracking. Local stresses and strains are the most important parameters for understanding the mechanism of underfill failures. As a result, the industry currently relies on the finite element method (FEM) to calculate the stress components, but the FEM may not be accurate enough compared to the actual stresses in underfill. FEM simulations require a careful consideration of important geometrical details and material properties. This thesis proposes a modeling approach that can accurately estimate the underfill delamination areas and crack trajectories, with the following three objectives. The first objective was to develop an experimental technique capable of measuring underfill deformations around the chip corner region. This technique combined confocal microscopy and the digital image correlation (DIC) method to enable tri-dimensional strain measurements at different temperatures, and was named the confocal-DIC technique. This techique was first validated by a theoretical analysis on thermal strains. In a test component similar to a flip-chip package, the strain distribution obtained by the FEM model was in good agreement with the results measured by the confocal-DIC technique, with relative errors less than 20% at chip corners. Then, the second objective was to measure the strain near a crack in underfills. Artificial cracks with lengths of 160 μm and 640 μm were fabricated from the chip corner along the 45° diagonal direction. The confocal-DIC-measured maximum hoop strains and first principal strains were located at the crack front area for both the 160 μm and 640 μm cracks. A crack model was developed using the extended finite element method (XFEM), and the strain distribution in the simulation had the same trend as the experimental results. The distribution of hoop strains were in good agreement with the measured values, when the model element size was smaller than 22 μm to capture the strong strain gradient near the crack tip. The third objective was to propose a modeling approach for underfill delamination and cracking with the effects of manufacturing variables. A deep thermal cycling test was performed on 13 test cells to obtain the reference chip-underfill delamination areas and crack profiles. An artificial neural network (ANN) was trained to relate the effects of manufacturing variables and the number of cycles to first delamination of each cell. The predicted numbers of cycles for all 6 cells in the test dataset were located in the intervals of experimental observations. The growth of delamination was carried out on FEM by evaluating the strain energy amplitude at the interface elements between the chip and underfill. For 5 out of 6 cells in validation, the delamination growth model was consistent with the experimental observations. The cracks in bulk underfill were modelled by XFEM without predefined paths. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5°. This approach met the goal of the thesis of estimating the underfill initial delamination, areas of delamination and crack paths in actual industrial flip-chip assemblies.Afin de protéger les interconnexions dans les assemblages, une couche de matériau d’underfill est utilisée pour remplir le volume et fournir un support mécanique entre la puce de silicium et le substrat. En raison de la géométrie du coin de puce et de l’écart du coefficient de dilatation thermique (CTE), l’underfill souffre d’une concentration de contraintes dans les coins lorsque la température est inférieure à la température de cuisson. Cette concentration de contraintes conduit à des défaillances mécaniques dans les encapsulations de flip-chip, telles que la délamination interfaciale puce-underfill et la fissuration d’underfill. Les contraintes et déformations locales sont les paramètres les plus importants pour comprendre le mécanisme des ruptures de l’underfill. En conséquent, l’industrie utilise actuellement la méthode des éléments finis (EF) pour calculer les composantes de la contrainte, qui ne sont pas assez précises par rapport aux contraintes actuelles dans l’underfill. Ces simulations nécessitent un examen minutieux de détails géométriques importants et des propriétés des matériaux. Cette thèse vise à proposer une approche de modélisation permettant d’estimer avec précision les zones de délamination et les trajectoires des fissures dans l’underfill, avec les trois objectifs suivants. Le premier objectif est de mettre au point une technique expérimentale capable de mesurer la déformation de l’underfill dans la région du coin de puce. Cette technique, combine la microscopie confocale et la méthode de corrélation des images numériques (DIC) pour permettre des mesures tridimensionnelles des déformations à différentes températures, et a été nommée le technique confocale-DIC. Cette technique a d’abord été validée par une analyse théorique en déformation thermique. Dans un échantillon similaire à un flip-chip, la distribution de la déformation obtenues par le modèle EF était en bon accord avec les résultats de la technique confocal-DIC, avec des erreurs relatives inférieures à 20% au coin de puce. Ensuite, le second objectif est de mesurer la déformation autour d’une fissure dans l’underfill. Des fissures artificielles d’une longueuer de 160 μm et 640 μm ont été fabriquées dans l’underfill vers la direction diagonale de 45°. Les déformations circonférentielles maximales et principale maximale étaient situées aux pointes des fissures correspondantes. Un modèle de fissure a été développé en utilisant la méthode des éléments finis étendue (XFEM), et la distribution des contraintes dans la simuation a montré la même tendance que les résultats expérimentaux. La distribution des déformations circonférentielles maximales était en bon accord avec les valeurs mesurées lorsque la taille des éléments était plus petite que 22 μm, assez petit pour capturer le grand gradient de déformation près de la pointe de fissure. Le troisième objectif était d’apporter une approche de modélisation de la délamination et de la fissuration de l’underfill avec les effets des variables de fabrication. Un test de cyclage thermique a d’abord été effectué sur 13 cellules pour obtenir les zones délaminées entre la puce et l’underfill, et les profils de fissures dans l’underfill, comme référence. Un réseau neuronal artificiel (ANN) a été formé pour établir une liaison entre les effets des variables de fabrication et le nombre de cycles à la délamination pour chaque cellule. Les nombres de cycles prédits pour les 6 cellules de l’ensemble de test étaient situés dans les intervalles d’observations expérimentaux. La croissance de la délamination a été réalisée par l’EF en évaluant l’énergie de la déformation au niveau des éléments interfaciaux entre la puce et l’underfill. Pour 5 des 6 cellules de la validation, le modèle de croissance du délaminage était conforme aux observations expérimentales. Les fissures dans l’underfill ont été modélisées par XFEM sans chemins prédéfinis. Les directions des fissures de bord étaient en bon accord avec les observations expérimentales, avec une erreur inférieure à 2,5°. Cette approche a répondu à la problématique qui consiste à estimer l’initiation des délamination, les zones de délamination et les trajectoires de fissures dans l’underfill pour des flip-chips industriels

    SETEC/Semiconductor Manufacturing Technologies Program: 1999 Annual and Final Report

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    Numerical analysis of lead-free solder joints: effects of thermal cycling and electromigration

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    To meet the requirements of miniaturization and multifunction in microelectronics, understanding of their reliability and performance has become an important research subject in order to characterise electronics served under various loadings. Along with the demands of the increasing miniaturization of electronic devices, various properties and the relevant thermo-mechanical-electrical response of the lead-free solder joints to thermal cycling and electro-migration become the critical factors, which affect the service life of microelectronics in different applications. However, due to the size and structure of solder interconnects in microelectronics, traditional methods based on experiments are not applicable in the evaluation of their reliability under complex joint loadings. This thesis presents an investigation, which is based on finite-element method, into the performance of lead-free solder interconnects under thermal fatigue and electro-migration, specifically in the areas as follows: (1) the investigation of thermal-mechanical performance and fatigue-life prediction of flip-chip package under different sizes to achieve a further understanding of IMC layer and size effects of a flip chip package under thermal cycling; (2) the establishment of a numerical method, simulating void-formation/crack-propagation based on the results of finite-element analysis, to allow the prediction of crack evolution and failure time for electro-migration reliability of solder bumps; (3) the establishment of a flow-based algorithm for combination effects of thermal-mechanical and electro-migration that was subsequent implemented in to an FE model to evaluate the reliability assessment of service lives associated with a flip chip package

    Development of convective reflow-projection moire warpage measurement system and prediction of solder bump reliability on board assemblies affected by warpage

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    Out-of-plane displacement (warpage) is one of the major thermomechanical reliability concerns for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may cause serious reliability problems. In this research, a convective reflow and projection moire warpage measurement system was developed. The system is the first real-time, non-contact, and full-field measurement system capable of measuring PWB/PWBA/chip package warpage with the projection moire technique during different thermal reflow processes. In order to accurately simulate the reflow process and to achieve the ideal heating rate, a convective heating system was designed and integrated with the projection moire system. An advanced feedback controller was implemented to obtain the optimum heating responses. The developed system has the advantages of simulating different types of reflow processes, and reducing the temperature gradients through the PWBA thickness to ensure that the projection moire system can provide more accurate measurements. Automatic package detection and segmentation algorithms were developed for the projection moire system. The algorithms are used for automatic segmentation of the PWB and assembled packages so that the warpage of the PWB and chip packages can be determined individually. The effect of initial PWB warpage on the fatigue reliability of solder bumps on board assemblies was investigated using finite element modeling (FEM) and the projection moire system. The 3-D models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different chip packages mounted on PWBs. The simulation results were validated and correlated with the experimental results obtained using the projection moire system and accelerated thermal cycling tests. Design of experiments and an advanced prediction model were generated to predict solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials. This study led to a better understanding of the correlation between PWB warpage and solder bump thermomechanical reliability on board assemblies.Ph.D.Committee Chair: Dr. Ume, I. Charles; Committee Member: Dr. Book, Wayne; Committee Member: Dr. Kim, Yeong; Committee Member: Dr. Pan, Jiahui; Committee Member: Dr. Sitaraman, Suresh; Committee Member: Dr. Wu, C. F. Jef

    FAILURE PREDICTION OF WIRE BONDS DUE TO FLEXURE

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    Solid state power modules are subjected to harsh environmental and operational loads. Identifying the potential design weakness and dominant failure mechanisms associated with the application is very critical to designing such power modules. Failure of the wedge-bonded wires is one of the most commonly identified causes of failures in power modules. This can occur when wires flex in response to a thermal cycling load. Since the heel of the wire is already weakened due to the ultrasonic bonding process, the flexing motion is enough to initiate a crack in the heel of the wire. Owing to the prevalence of this failure mechanism in power modules, a generalized first-order physics-of-failure based model has been developed to quantify these flexural/bending stresses. A variational calculus approach has been employed to determine the minimum energy wire profiles. The difference in curvatures corresponding to the wire profiles before and after thermal cycling provide the flexural stresses. The stresses/strains determined from the load transformation model are then used in a damage model to determine the cycles to failure. The model has been validated against temperature cycling test results. The effects of residual stresses, that are introduced during the loop formation, (on the thermal cycling life) of these wires also has been studied. It is believed that the ultrasonic wirebonding process renders the wires weaker at the heel. Efforts have been made to simulate the wirebonding mechanism using Finite element analysis. The key parameters that influence the wirebonding process are identified. Flexural stresses are determined for various heel cross-sectional profiles that correspond to different bond forces. Additional design constraints may prevent some of the wedge-bonded wires from being aligned parallel to the bond pads. The influence of having the bond pads with a non-zero width offset has been studied through finite element simulations. The 3D minimum energy wire profiles used in the modeling has been obtained through a new energy minimization based model

    Thermomechanical Design Rules for the Development of Photovoltaic Modules

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    Health Condition Assessment of Multi-Chip IGBT Module with Magnetic Flux Density

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    To achieve efficient conversion and flexible control of electronic energy, insulated gate bipolar transistor (IGBT) power modules as the dominant power semiconductor devices are increasingly applied in many areas such as electric drives, hybrid electric vehicles, railways, and renewable energy systems. It is known that IGBTs are the most vulnerable components in power converter systems. To achieve high power density and high current capability, several IGBT chips are connected in parallel as a multi-chip IGBT module, which makes the power modules less reliable due to a more complex structure. The lowered reliability of IGBT modules will not only cause safety problems but also increase operation costs due to the failure of IGBT modules. Therefore, the reliability of IGBTs is important for the overall system, especially in high power applications. To improve the reliability of IGBT modules, this thesis proposes a new health state assessment model with a more sensitive precursor parameter for multi-chip IGBT module that allows for condition-based maintenance and replacement prior to complete failure. Accurate health condition monitoring depends on the knowledge of failure mechanism and the selection of highly sensitive failure precursor. IGBT modules normally wear out and fail due to thermal cycling and operating environment. To enhance the understanding of the failure mechanism and the external characteristic performance of multi-chip IGBT modules, an electro-thermal finite element model (FEM) of a multi-chip IGBT module used in wind turbine converter systems was established with considerations for temperature dependence of material property, the thermal coupling effect between components, and the heat transfer process. The electro-thermal FEM accurately performed temperature distribution and the distribution electrical characteristic parameters during chip solder degradation. This study found an increased junction temperature, large change of temperature distribution, and more serious imbalanced current sharing during a single chip solder aging, thereby accelerating the aging of the whole IGBT module. According to the change of thermal and electrical parameters with chip solder fatigue, the sensitivity of fatigue sensitive parameters (FSPs) was analyzed. The collector current of the aging chip showed the highest sensitivity with the chip solder degradation compared with the junction temperature, case temperature, and collector-emitter voltage. However, the current distribution of internal components remains inaccessible through direct measurements or visual inspection due to the package. As the relationship between the current and magnetic field has been studied and gradually applied in sensor technologies, magnetic flux density was proposed instead of collector current as a new precursor for health condition monitoring. Magnetic flux density distribution was extracted by an electro-thermal-magnetic FEM of the multi-chip IGBT module based on electromagnetic theory. Simulation results showed that magnetic flux density had even higher sensitivity than collector current with chip solder degradation. In addition, the magnetic flux density was only related with the current and was not influenced by temperature, which suggested good selectivity. Therefore, the magnetic flux density was selected as the precursor due to its better sensitivity, selectivity, and generality. Finally, a health state assessment model based on backpropagation neural network (BPNN) was established according to the selected precursor. To localize and evaluate chip solder degradation, the health state of the IGBT module was determined by the magnetic flux density for each chip and the corresponding operating conduction current. BPNN featured good self-learning, self-adapting, robustness and generalization ability to deal with the nonlinear relationship between the four inputs and health state. Experimental results showed that the proposed model was accurate and effective. The health status of the IGBT modules was effectively recognized with an overall recognition rate of 99.8%. Therefore, the health state assessment model built in this thesis can accurately evaluate current health state of the IGBT module and support condition-based maintenance of the IGBT module
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