MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

Diamond Schottky barrier diodes

Research on wide band gap semiconductors suitable for power electronic devices has spread rapidly in the last decade. The remarkable results exhibited by silicon carbide (SiC) Schottky batTier diodes (SBDs), commercially available since 2001, showed the potential of wide band gap semiconductors for replacing silicon (Si) in the range of medium to high voltage applications, where high frequency operation is required. With superior physical and electrical properties, diamond became a potential competitor to SiC soon after Element Six reported in 2002 the successful synthesis of single crystal plasma deposited diamond with high catTier mobility. This thesis discusses the remarkable properties of diamond and introduces several device structures suitable for power electronics. The calculation of several figures of merit emphasize the advantages of diamond with respect to silicon and other wide band gap semiconductors and clearly identifies the areas where its impact would be most significant. Information regarding the first synthesis of diamond, which took place back in 1954, together with data regarding the modern technological process which leads nowadays to high-quality diamond crystals suitable for electronic devices, are reviewed. Models regarding the incomplete ionization of atomic dopants and the variation of catTier mobility with doping level and temperature have been elaborated and included in numerical simulators. The study introduces the novel diamond M-i-P Schottky diode, a version of power Schottky diode which takes advantage of the extremely high intrinsic hole mobility. The structure overcomes the drawback induced by the high activation energies of acceptor dopants in diamond which yield poor hole concentration at room temperature. The complex shape of the on-state characteristic exhibited by diamond M-i-P Schottky structures is thoroughly investigated by means of experimental results, numerical simulations and theoretical considerations. The fabrication of a ramp oxide termination on a diamond device is for the first time reported in this thesis. Both experimental and simulated results show the potential of this termination structure, previously built on Si and SiC power devices. A comprehensive comparison between the ramp oxide and two other versions of the field plate termination concept, the single step and the three-step structures, has been performed, considering aspects such as electrical performance, occupied area, complexity of technological process and cost. Based on experimental results presented in this study, together with predictions made via simulations and theoretical models, it is concluded that diamond M-i-P Schottky diodes have the ability to deliver significantly higher performance compared to that of SiC SBDs if issues such as material defects, Schottky contact formation and measurement of reliable ionization coefficients are carefully addressed in the near future

Fabrication, characterization, and modeling of organic capacitors, Schottky diodes, and field effect transistors

The objectives of this project are to fabricate, characterize, and model organic microelectronic devices by traditional lithography techniques and Technology Computer Aided Design (TCAD). Organic microelectronics is becoming a promising field due to its number of advantages in low-cost fabrication for large area substrates. There have been growing studies in organic electronics and optoelectronics. In this project, several organic microelectronic devices are studied with the aid of experimentation and numerical modeling. Organic metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) capacitors consisting of insulating polymer poly(4-vinylphenol) (PVP) have been fabricated by spin-coating, photo lithography, and reactive ion etching techniques. Based on the fabricated devices, the dielectric constant of the (PVP) is calculated to be about 5.6–5.94. The MIS capacitor consisting of organic semiconductor pentacene has been investigated. The hole concentration of pentacene is determined to be around 8 × 1016 cm −3. Schottky diodes consisting of aluminum and a layer of p-type semiconducting polymer poly[2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV) have been fabricated. Based on the current-voltage (I-V) and capacitance-voltage (C-V) measurements, the temperature dependence of hole mobility in MEH-PPV has been extracted by the space-charge limited conduction (SCLC) model, from 300 to 400 K. Moreover, the value of the effective hole density for MEH-PPV has been determined to be 2.24 × 1017 cm−3. Numerical simulations have been carried out to identify the parameters which affect the performance of devices significantly. Organic n- and p-channel field-effect transistors (FETs) have been designed and fabricated. By using Naphthalene-tetracarboxylic-dianhydride (NTCDA) as an organic semiconductor, n-channel FETs have been fabricated and characterized. At room temperature, the device characteristics have displayed electron mobility of 0.016 cm2/Vs, threshold voltage of −32 V, and on/off ratio of 2.25 × 102. Pentacene, an organic semiconductor offering high device performance, has been employed to fabricate the p-channel FETs. At room temperature, the device characteristics have displayed hole mobility of 0.26 cm2/Vs, threshold voltage of −3.5 V, subthreshold slope of 2.5 V/decade, and on/off ratio of 105. The temperature and field dependence of mobility has been studied based on the experimental results. Based on numerical simulations, the influence of bulk traps has also been identified, and the field-dependent mobility model has been used to obtain more accurate simulation results. Furthermore, electrostatically assembled monolayer (poly(dimethyldiallylammonium chloride) (PDDA)) is introduced at the organic/insulator interface to improve the performance of the FETs. The efforts carried out in this work appear to be the first reported attempt at the investigation of the temperature dependence of mobility for the given organic devices, and the surface modification of organic FETs by electrostatically assembled monolayer