Digital fringe projection system for measuring warpage of painted and unpainted PBGAs and boards and FEA studies of PBGA warpage

Improvements in chip package technologies have led to smaller package sizes and higher density circuitry that require superior reliability of chip packages. One of the crucial factors affecting the reliability of chip packages is warpage which primarily occurs during the reflow process. Because warpage may cause serious reliability problems such as solder bump failure and die cracking, warpage control has become a crucial task. Advancements in warpage measurement and prediction would provide important steps toward addressing this concern. Among the various warpage measurement techniques, fringe projection techniques (i.e., laser fringe projection (LFP) and digital fringe projection (DFP)) have emerged as recent trends due to their non-contact, full-field, and high-resolution (for small viewing area) capabilities for measuring the warpage of chip packages and boards (i.e., printed wiring boards (PWBs) and PWB assemblies). In this research, the measurement capabilities of a LFP system were improved by reducing its laser speckle noise and post-processing time, and a novel DFP system for measuring the warpage of painted and unpainted chip packages and boards was developed. Also, parametric studies were performed to predict the warpage of plastic ball grid array packages affected by four geometric factors. Finally, a guideline that manufacturing engineers can use for selecting the most suitable warpage measurement technique for their particular application was developed. The results of this study will help to improve the yields and reliability of chip packages and boards, reduce the manufacturing costs and time to market for chip packages and boards and ultimately reduce the prices of end-products.Ph.D

Study and characetrization of plastic encapsulated packages for MEMS

Technological advancement has thrust MEMS design and fabrication into the forefront of modern technologies. It has become sufficiently self-sustained to allow mass production. The limiting factor which is stalling commercialization of MEMS is the packaging and device reliability. The challenging issues with MEMS packaging are application specific. The function of the package is to give the MEMS device mechanical support, protection from the environment, and electrical connection to other devices in the system. The current state of the art in MEMS packaging transcends the various packaging techniques available in the integrated circuit (IC) industry. At present the packaging of MEMS includes hermetic ceramic packaging and metal packaging with hermetic seals. For example the ADXL202 accelerometer from the Analog Devices. Study of the packaging methods and costs show that both of these methods of packaging are expensive and not needed for majority of MEMS applications. Due to this the cost of current MEMS packaging is relatively high, as much as 90% of the finished product. Reducing the cost is therefore of the prime concern. This Thesis explores the possibility of an inexpensive plastic package for MEMS sensors like accelerometers, optical MEMS, blood pressure sensors etc. Due to their cost effective techniques, plastic packaging already dominates the IC industry. They cost less, weigh less, and their size is small. However, porous nature of molding materials allows penetration of moisture into the package. The Thesis includes an extensive study of the plastic packaging and characterization of three different plastic package samples. Polymeric materials warp upon absorbing moisture, generating hygroscopic stresses. Hygroscopic stresses in the package add to the thermal stress due to high reflow temperature. Despite this, hygroscopic characteristics of the plastic package have been largely ignored. To facilitate understanding of the moisture absorption, an analytical model is presented in this Thesis. Also, an empirical model presents, in this Thesis, the parameters affecting moisture ingress. This information is important to determine the moisture content at a specific time, which would help in assessing reliability of the package. Moisture absorption is modeled using the single phase absorption theory, which assumes that moisture diffusion occurs freely without any bonding with the resin. This theory is based on the Fick\u27s Law of diffusion, which considers that the driving force of diffusion is the water concentration gradient. A finite difference simulation of one-dimensional moisture diffusion using the Crank-Nicolson implicit formula is presented. Moisture retention causes swelling of compounds which, in turn, leads to warpage. The warpage induces hygroscopic stresses. These stresses can further limit the performance of the MEMS sensors. This Thesis also presents a non invasive methodology to characterize a plastic package. The warpage deformations of the package are measured using Optoelectronic holography (OEH) methodology. The OEH methodology is noninvasive, remote, and provides results in full-field-of-view. Using the quantitative results of OEH measurements of deformations of a plastic package, pressure build up can be calculated and employed to assess the reliability of the package

Study Of Wave Soldering Using Thermal-Fluid Structure Interaction Technique On Pin Through Hole In Printed Circuit Board

Wave soldering is one of the most familiar and well-established processes in the electronics assembly industry, which is used to assemble the pin-through hole (PTH) component onto the printed circuit board (PCB). The solder joint defects such as cracks, void formation, and incomplete filling of the PCB hole may weaken the PTH solder joint. In the present research, the PTH vertical fill was carried out experimentally by using a newly developed adjustable fountain wave soldering machine (0° conveyor angle). A similar PCB and components were assembled by using a conventional wave soldering machine (6° conveyor angle). A non-destructive X-ray computed tomographyscanning machine was employed to inspect the vertical fill of each solder joint. On the other hand, the wave soldering process considering thermal-FSI phenomenon was the focus on this research. The thermal-FSI simulation was carried out by using finite volume (FLUENT) and finite element (ABAQUS) based software through the real time coupling technique using Mesh-based parallel Code Coupling Interface (MpCCI) software. It was found that the adjustable fountain wave soldering yielded higher vertical fill (~99.4%) than the conventional wave soldering machine (~90.8%). Apart from that, the simulations were broadening to the parametric studies on various process and design factors such as conveyor angle and PTH geometry (i.e. offset position, shape, diameter,offset angle). The influences of these parameters on the fluid flow distribution, structural displacement, pressure distribution, and stress have been highlighted. Moreover the optimization of PTH connector in the wave soldering process using response surface methodology (RSM) was handled to study the interactive relationship between independent variables to the responses. The optimum geometrical and process parameters for the PCB and PTH connector were characterized by 0.12 mm of PTH offset position, 0.17 mm of PTH diameter, 0o of offset angle and 473.15 K of molten solder temperature. Finally the case study on the effects of PCB configuration during wave soldering was investigated. Five PCB configurations were considered based on the position of the components. Results show that PCB component configurations significantly influence the PCB and yield unfavorable deformation and stress. The research findings are expected to be significant contributions in for the microelectronic industr

Lifetime modelling of large area solder joints in power electronic inverter units

Power electronics (PE) modules in inverter units are a critical part of the Hybrid/Electric vehicles drivetrain. During passive temperature cycling, the solder joint between the PE module and the baseplate develops cracks. A detailed reliability investigation was carried out on multiple physical variants under three temperature cycling profiles to uncover major influence parameters. A stress triaxiality and inelastic strain based FEM damage parameter was formulated which showed excellent correlation with experimental results.Leistungselektronikmodule (PE) in Wechselrichtern sind ein wichtiger Bestandteil von Hybrid-/Elektrofahrzeugen. Bei passivem Temperaturwechsel entwickelt die Lötstelle zwischen dem PE-Modul und der Grundplatte Risse. Es wurde eine detaillierte Zuverlässigkeitsuntersuchung an mehreren physikalischen Varianten unter drei Temperaturwechselprofile durchgeführt, um die wichtigsten Einflussparameter aufzudecken. Es wurde ein auf Spannungs-Triaxialität und unelastischer Dehnung basierender FEM-Schadensparameter formuliert, der eine ausgezeichnete Korrelation mit experimentellen Ergebnissen zeigte

Evaluation of solder-joint reliability for a 10mm Quad Flat Leadless package with top-side paddle using classical models for a leadless device and accelerated life testing

The standard QFN package consists of a leadless perimeter array and a bottom solderable thermal paddle. The thermal performance of the package can be improved by moving the paddle to the topside. The soldered surface area of the package reduces by about 80% with a top-side paddle. The soldered-joint life will also reduce due to the significant thermal coefficient of expansion mismatch between the QFN package and the circuit board. The solder-joint reliability of a large QFN package with top-side paddle is not well understood. This thesis evaluates the solder-joint reliability of a 10mm square leadless QFN package with top-side paddle. The analysis includes several classical models for a leadless package and compares modeling results to accelerated reliability testing. The accelerated tests include the influence mold compound and lead finish play on solder-joint life and ways to improve solder-joint reliability

Mechanical characterization and modeling of solder joints for the secondary side reflow of large IC packages

As the drive continues to reduce the size of Printed Wiring Assemblies (PWAs), improve performance of electronic assemblies, and reduce costs of these products, reliable secondary (bottom) side reflow operations must be developed. Attaching Surface Mount Technology (SMT) components to the secondary side of a Printed Circuit Board (PCB) is accomplished by placing components on the PCB's secondary side and processing it through the reflow oven at this point. This board is then flipped over so that more components can be placed on the side that is facing up (primary side). The PCB must again be processed through the reflow oven. Large Integrated Circuit (IC) packages that are soldered to the secondary side fall off of the PCB during reflow of the primary side. Intuition may lead one to believe this is caused solely by weight, size, etc., but experienced personnel are not able to consistently predict which components will fail. The purpose of this work is to convey the necessary knowledge to explain and predict the behavior of components during Secondary Side Reflow (SSR). This thesis will ultimately present a method by which guidelines for SSR can be created. Currently, SSR is limited to small passive devices and small Integrated Circuit (IC) packages. It is anticipated that future PWA designs will require large ICs such as Quad Flat Packs (QFP) and Ball Grid Arrays (BGA) on the secondary side. A large variety of SMT components are available, but the focus of this research was directed towards large IC packages. Current manufacturing guidelines for such products do not exist and development of these are imperative if a costly trial and error approach is to be avoided. In an environment where product technology advancement and cost reduction are key to survival, industry must develop and understand this manufacturing process. Cost savings from SSR will be most directly realized with compressed product development cycles, reduced use of PCBs, components, and raw materials, and more efficient use of manufacturing capital and employees. These cost savings would be realized nearly immediately after a set of manufacturing guidelines is developed

Numerical Parametric Study of the Thermomechanical Effect of Encapsulation on a Welded Beam Lead Component

Encapsulation of components and assemblies has become widespread in the design of electronic products, providing protection from the environment and enhancing reliability. In this thesis, computational simulations are used to parametrically investigate the thermomechanical role played by the encapsulant when a beam-lead component is welded to slender copper busbars, encapsulated in a polymeric encapsulant, and subjected to temperature cycling. The parametric studies are conducted in two phases, using simplified two-dimensional finite element models. In the first phase, a parametric design space is generated to systematically vary the encapsulant's thermomechanical properties, namely the Young's modulus and Coefficient of Thermal Expansion. A gull wing geometry is introduced into the lead of the component as a stress relief feature. In this case, a ramp thermal loading profile is used to understand the physics of this design and to provide relative comparisons between different combinations of the encapsulant's material properties within the design space. Response surface models are generated over the design space. In the second phase, a Taguchi Design of Experiments (DOE) approach, based on orthogonal arrays, is used to analyze the effects of multiple design parameters under cyclic thermal loading. This includes encapsulant properties (a subset of the properties investigated in the first phase), encapsulant dimensions, lead geometry and dimensions, and busbar dimensions. Lead geometry is considered with and without stress relief features. The loading used in this phase is three temperature cycles between -40oC and 90oC. The primary areas of concern (response variables) in both studies are the component lead and interconnect regions. Deformation and stress states in these critical regions are compared. Main factor effects and selected parameter interactions are computed in accordance with the Taguchi orthogonal arrays, to understand the dominant parameters and parameter interactions for cyclic thermomechanical stresses in this encapsulated assembly

Non-destructive evaluation of solder joint reliability

A through life non-destructive evaluation technique is presented in which a key solder joint feature, nucleating at the bump to silicon interface and propagating across a laminar crack plane is captured and tracked using acoustic microscopy imaging (AMI). The feasibility of this concept was successfully demonstrated by employing the measurement technique in combination with Finite Element Analysis (FEA) to study the impact of component floor plan layout on the reliability of electronics systems subjected to thermal cycling. A comprehensive review of current and emerging packaging and interconnect technologies has shown increasingly a move from conventional 2D to 3D packaging. These present new challenges for reliability and Non Destructive Evaluation (NDE) due to solder joints being hidden beneath the packaging, and not ordinarily visible or accessible for inspection. Solutions are developed using non-destructive testing (NDT) techniques that have the potential to detect and locate defects in microelectronic devices. This thesis reports on X-ray and Acoustic Micro Imaging (AMI) which have complementary image discriminating features. Gap type defects are hard to find using X-ray alone due to low contrast and spot size resolution, whereas AMI having better axial resolution has allowed cracks and delamination at closely spaced interfaces to be investigated. The application of AMI to the study of through life solder joint behaviour has been achieved for the first time. Finite Element Analysis and AMI performance were compared to measure solder joint reliability for several realistic test cases. AMI images were taken at regular intervals to monitor through- life behaviour. Image processing techniques were used to extract a diameter measurement for a laminar crack plane, within a solder joint damage region occurring at the bump to silicon interface. FEA solder joint reliability simulations for flip-chip and micro-BGA (mBGA) packages placed on FR4 PCB's were compared to the AMI measurement performance, with a reasonable level of correlation observed. Both techniques clearly showed significant reliability degradation of the critical solder joints located furthest from the neutral axis of the package, typically residing at the package corners. The technique also confirmed that circuit board thickness can affect interconnect reliability, as can floor plan. Improved correlation to the real world environment was achieved when simulation models considered the entire floor plan layout and constraints imposed on the circuit board assembly. This thesis established a novel through life solder joint evaluation method crucial to the development of better physics of failure models and the advancement of model based prognostics in electronics systems

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies