Subthreshold design of ultra low-power analog modules

Il consumo di potenza rappresenta l’indicatore chiave delle performance di recenti applicazioni portatili, come dispositivi medici impiantabili o tag RFID passivi, allo scopo di aumentare, rispettivamente, i tempi di funzionamento o i range operativi. La riduzione della tensione di alimentazione si è dimostrata l’approccio migliore per ridurre il consumo di potenza dei sistemi digitali integrati. Al fine di tenere il passo con la riduzione delle tensioni di alimentazione, anche le sezioni analogiche dei sistemi mixed signal devono essere in grado di funzionare con livelli di tensione molto bassi. Di conseguenza, sono richieste nuove metodologie di progettazione analogica e configurazioni circuitali innovative in grado di lavorare con tensioni di alimentazioni bassissime, dissipando una potenza estremamente bassa. Il regime di funzionamento sottosoglia consente di ridurre notevolmente le tensioni applicabili ai dispositivi ed si contraddistingue per i livelli di corrente molto bassi, rispetto al ben noto funzionamento in forte inversione. Queste due caratteristiche sono state sfruttate nella realizzazione di moduli analogici di base ultra low voltage, low power. Tre nuove architetture di riferimenti di tensione, che lavorano con tutti i transistor polarizzati in regime sottosoglia, sono stati fabbricati in tecnologia CMOS 0.18 μm. I tre circuiti si basano sullo stesso principio di funzionamento per compensare gli effetti della variazione della temperatura sulla tensione di riferimento generata. Tramite il principio di funzionamento proposto, la tensione di riferimento può essere approssimata con la differenza delle tensioni di soglia, a temperatura ambiente, dei transistor. Misure sperimentali sono state effettuate su set con più di 30 campioni per ogni configurazione circuitale. Una dettagliata analisi statistica ha dimostrato un consumo medio di potenza che va da pochi nano watt a poche decine di nano watt, mentre la minima tensione di alimentazione, raggiunta da una delle tre configurazioni, è di soli 0.45 V. Le tensioni di riferimento generate sono molto precise rispetto alle variazioni della temperatura e della tensione di alimentazione, infatti sono stati ottenuti coefficienti di temperatura e line sensitivity medi a partire rispettivamente da 165 ppm/°C e 0.065 %/V. Inoltre, è stata trattata anche la progettazione di amplificatori ultra low voltage, low power. Sono state illustrate linee guida dettagliate per la progettazione di amplificatori sottosoglia e le stesse sono state applicate per la realizzazione di un amplificatore a due stadi, con compensazione di Miller, funzionante con una tensione di alimentazione di 0.5 V. I risultati sperimentali dell’op amp proposto, fabbricato in tecnologia CMOS 0.18 μm, hanno mostrato un guadagno DC ad anello aperto di 70 dB, un prodotto banda guadagno di 18 kHz ed un consumo di potenza di soli 75 nW. I risultati delle misure sperimentali dimostrano che gli amplificatori operazionali in sottosoglia rappresentano una soluzione molto interessante nella realizzazione di applicazioni efficienti in termini energetici per gli attuali sistemi elettronici portatili. Dal confronto con amplificatori ultra low power, low voltage presenti in letteratura, si evince che la soluzione proposta offre un miglior compromesso tra velocità, potenza dissipata e capacità di carico

Analog VLSI Circuits for Biosensors, Neural Signal Processing and Prosthetics

Stroke, spinal cord injury and neurodegenerative diseases such as ALS and Parkinson's debilitate their victims by suffocating, cleaving communication between, and/or poisoning entire populations of geographically correlated neurons. Although the damage associated with such injury or disease is typically irreversible, recent advances in implantable neural prosthetic devices offer hope for the restoration of lost sensory, cognitive and motor functions by remapping those functions onto healthy cortical regions. The research presented in this thesis is directed toward developing enabling technology for totally implantable neural prosthetics that could one day restore lost sensory, cognitive and motor function to the victims of debilitating neural injury or disease. There are three principal components to this work. First, novel integrated biosensors have been designed and implemented to transduce weak extra-cellular electrical potentials and optical signals from cells cultured directly on the surface of the sensor chips, as well as to manipulate cells on the surface of these chips. Second, a method of detecting and identifying stereotyped neural signals, or action potentials, has been mapped into silicon circuits which operate at very low power levels suitable for implantation. Third, as one small step towards the development of cognitive neural implants, a learning silicon synapse has been implemented and a neural network application demonstrated. The original contributions of this dissertation include: * A contact image sensor that adapts to background light intensity and can asynchronously detect statistically significant optical events in real-time; * Programmable electrode arrays for enhanced electrophysiological recording, for directing cellular growth, for site-specific in situ bio-functionalization, and for analyte and particulate collection; * Ultra-low power, programmable floating gate template matching circuits for the detection and classification of neural action potentials; * A two transistor synapse that exhibits spike timing dependent plasticity and can implement adaptive pattern classification and silicon learning

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

Contributions to the design of power modules for electric and hybrid vehicles: trends, design aspects and simulation techniques

314 p.En la última década, la protección del medio ambiente y el uso alternativo de energías renovables están tomando mayor relevancia tanto en el ámbito social y político, como científico. El sector del transporte es uno de los principales causantes de los gases de efecto invernadero y la polución existente, contribuyendo con hasta el 27 % de las emisiones a nivel global. En este contexto desfavorable, la electrificación de los vehículos de carretera se convierte en un factor crucial. Para ello, la transición de la actual flota de vehículos de carretera debe ser progresiva forzando la investigación y desarrollo de nuevos conceptos a la hora de producir vehículos eléctricos (EV) y vehículos eléctricos híbridos (HEV) más eficientes, fiables, seguros y de menor coste. En consecuencia, para el desarrollo y mejora de los convertidores de potencia de los HEV/EV, este trabajo abarca los siguientes aspectos tecnológicos: - Arquitecturas de la etapa de conversión de potencia. Las principales topologías que pueden ser implementadas en el tren de potencia para HEV/EV son descritas y analizadas, teniendo en cuenta las alternativas que mejor se adaptan a los requisitos técnicos que demandan este tipo de aplicaciones. De dicha exposición se identifican los elementos constituyentes fundamentales de los convertidores de potencia que forman parte del tren de tracción para automoción.- Nuevos dispositivos semiconductores de potencia. Los nuevos objetivos y retos tecnológicos solo pueden lograrse mediante el uso de nuevos materiales. Los semiconductores Wide bandgap (WBG), especialmente los dispositivos electrónicos de potencia basados en nitruro de galio (GaN) y carburo de silicio (SiC), son las alternativas más prometedoras al silicio (Si) debido a las mejores prestaciones que poseen dichos materiales, lo que permite mejorar la conductividad térmica, aumentar las frecuencias de conmutación y reducir las pérdidas.- Análisis de técnicas de rutado, conexionado y ensamblado de módulos de potencia. Los módulos de potencia fabricados con dies en lugar de dispositivos discretos son la opción preferida por los fabricantes para lograr las especificaciones indicadas por la industria de la automoción. Teniendo en cuenta los estrictos requisitos de eficiencia, fiabilidad y coste es necesario revisar y plantear nuevos layouts de las etapas de conversión de potencia, así como esquemas y técnicas de paralelización de los circuitos, centrándose en las tecnologías disponibles.Teniendo en cuenta dichos aspectos, la presente investigación evalúa las alternativas de semiconductores de potencia que pueden ser implementadas en aplicaciones HEV/EV, así como su conexionado para la obtención de las densidades de potencia requeridas, centrándose en la técnica de paralelización de semiconductores. Debido a la falta de información tanto científica como comercial e industrial sobre dicha técnica, una de las principales contribuciones del presente trabajo ha sido la propuesta y verificación de una serie de criterios de diseño para el diseño de módulos de potencia. Finalmente, los resultados que se han extraído de los circuitos de potencia propuestos demuestran la utilidad de dichos criterios de diseño, obteniendo circuitos con bajas impedancias parásitas y equilibrados eléctrica y térmicamente. A nivel industrial, el conocimiento expuesto en la presente tesis permite reducir los tiempos de diseño a la hora de obtener prototipos de ciertas garantías, permitiendo comenzar la fase de prototipado habiéndose realizado comprobaciones eléctricas y térmicas

Circuit techniques for low-voltage and high-speed A/D converters

The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.reviewe

Improving the mechanistic study of neuromuscular diseases through the development of a fully wireless and implantable recording device

Neuromuscular diseases manifest by a handful of known phenotypes affecting the peripheral nerves, skeletal muscle fibers, and neuromuscular junction. Common signs of these diseases include demyelination, myasthenia, atrophy, and aberrant muscle activity—all of which may be tracked over time using one or more electrophysiological markers. Mice, which are the predominant mammalian model for most human diseases, have been used to study congenital neuromuscular diseases for decades. However, our understanding of the mechanisms underlying these pathologies is still incomplete. This is in part due to the lack of instrumentation available to easily collect longitudinal, in vivo electrophysiological activity from mice. There remains a need for a fully wireless, batteryless, and implantable recording system that can be adapted for a variety of electrophysiological measurements and also enable long-term, continuous data collection in very small animals. To meet this need a miniature, chronically implantable device has been developed that is capable of wirelessly coupling energy from electromagnetic fields while implanted within a body. This device can both record and trigger bioelectric events and may be chronically implanted in rodents as small as mice. This grants investigators the ability to continuously observe electrophysiological changes corresponding to disease progression in a single, freely behaving, untethered animal. The fully wireless closed-loop system is an adaptable solution for a range of long-term mechanistic and diagnostic studies in rodent disease models. Its high level of functionality, adjustable parameters, accessible building blocks, reprogrammable firmware, and modular electrode interface offer flexibility that is distinctive among fully implantable recording or stimulating devices. The key significance of this work is that it has generated novel instrumentation in the form of a fully implantable bioelectric recording device having a much higher level of functionality than any other fully wireless system available for mouse work. This has incidentally led to contributions in the areas of wireless power transfer and neural interfaces for upper-limb prosthesis control. Herein the solution space for wireless power transfer is examined including a close inspection of far-field power transfer to implanted bioelectric sensors. Methods of design and characterization for the iterative development of the device are detailed. Furthermore, its performance and utility in remote bioelectric sensing applications is demonstrated with humans, rats, healthy mice, and mouse models for degenerative neuromuscular and motoneuron diseases

Delta STATCOM with partially rated energy storage for intended provision of ancillary services

This thesis presents research on two distinct areas, where the work carried out in the first half highlights the challenges posed by the declining system inertia in the future power systems and the potential capability of the energy storage systems in bridging the gap, supporting a safe and reliable operation. A comparison of various energy storage technologies based on their specific energy, specific power, response time, life-cycle, efficiency, cost and further correlating these characteristics to the timescale requirements of frequency and RoCoF services showed that supercapacitors (SC) and Li-ion batteries present the most suitable candidates. Results of a network stability study showed that for a power system rated at 2940 MVA with a high RES contribution of 1688 MVA, equating to 57% of the energy mix, during a power imbalance of 200 MW, an ESS designed to provide emulated inertia response (EIR) in isolation required a power and energy rating of 39.54 MW and 0.0365 MWh respectively. Similarly, providing primary frequency response (PFR) on its own required a power and energy rating of 114.52 MW and 2.14 MWh respectively. ESS providing these services in isolation was not able to maintain all the frequency operating limits and similar results were also seen in the case of the recently introduced Dynamic Containment service. However, with the introduction of a combined response capability, a significantly improved performance, comparable to that of the synchronous generators was observed. In order to maintain the RoCoF and the statutory frequency limit of 0.5 Hz/s and ±0.5 Hz respectively, an ESS must be able to respond with a delay time of no more than 0.2 seconds and be able to ramp up to full response within 0.3 seconds (0.5 seconds from the start of contingency) for a frequency deviation of ±0.5 Hz. The second half of the thesis focused on investigating the current state-of-the-art power conversion system topologies, with the objective of identifying a suitable topology for interfacing ESSs to the grid at MV level. A delta-connected Modular Multilevel STATCOM with partially rated storage (PRS-STATCOM) is proposed, capable of providing both reactive and active power support. The purpose is to provide short-term energy storage enabled grid support services such as inertial and frequency response, either alongside or temporarily instead of standard STATCOM voltage support. The topology proposed here contains two types of sub-modules (SM) in each phase-leg: standard sub-modules (STD-SMs) and energy storage element sub-modules (ESE-SMs) with a DC-DC interface converter between the SM capacitor and the ESE. A control structure has been developed that allows energy transfer between the SM capacitor and the ESE, resulting in an active power exchange between the converter and the grid. A 3rd harmonic current injection into the converter waveforms was used to increase the amount of power that can be extracted from the ESE-SMs and so reduce the required ESE-SMs fraction in each phase-leg. Simulation results demonstrate that for three selected active power ratings, 1 pu, 2/3 pu, & 1/3 pu, the fraction of SMs that need to be converted to ESE-SMs are only 69%, 59% & 38%. Thus, the proposed topology is effective in adding real power capability to a STATCOM without a large increase in equipment cost. Furthermore, modifying the initially proposed topology with the use of Silicon Carbide (SiC) switching devices and interleaved DC-DC interface converter with inverse coupled inductors resulted in similar efficiencies when operated in STATCOM mode.Open Acces