Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation

IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC

This work presents IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling analog-to-digital converter using a built-in current sensor [BICS]. Gate-drain, source-drain, gate-source and gate-substrate bridging faults are injected using fault injection transistors. All the four faults cause varying fault currents and are successfully detected by the BICS at a good operation speed. The BICS have a negligible impact on the performance of the modulator and an external pin is provided to completely cut-off the BICS from the modulator. The modulator was designed and fabricated in 1.5 μm n-well CMOS process. The decimator was designed on Altera\u27s FLEXE20K board using Verilog. The modulator and decimator were assembled together to form a sigma-delta ADC

Optimal Sharpening of Compensated Comb Decimation Filters: Analysis and Design

Comb filters are a class of low-complexity filters especially useful for multistage decimation processes. However, the magnitude response of comb filters presents a droop in the passband region and low stopband attenuation, which is undesirable in many applications. In this work, it is shown that, for stringent magnitude specifications, sharpening compensated comb filters requires a lower-degree sharpening polynomial compared to sharpening comb filters without compensation, resulting in a solution with lower computational complexity. Using a simple three-addition compensator and an optimization-based derivation of sharpening polynomials, we introduce an effective low-complexity filtering scheme. Design examples are presented in order to show the performance improvement in terms of passband distortion and selectivity compared to other methods based on the traditional Kaiser-Hamming sharpening and the Chebyshev sharpening techniques recently introduced in the literature

High-Precision Measurement of Sine and Pulse Reference Signals using Software-Defined Radio

This paper addresses simultaneous, high-precision measurement and analysis of generic reference signals by using inexpensive commercial off-the-shelf Software Defined Radio hardware. Sine reference signals are digitally down-converted to baseband for the analysis of phase deviations. Hereby, we compare the precision of the fixed-point hardware Digital Signal Processing chain with a custom Single Instruction Multiple Data (SIMD) x86 floating-point implementation. Pulse reference signals are analyzed by a software trigger that precisely locates the time where the slope passes a certain threshold. The measurement system is implemented and verified using the Universal Software Radio Peripheral (USRP) N210 by Ettus Research LLC. Applying standard 10 MHz and 1 PPS reference signals for testing, a measurement precision (standard deviation) of 0.36 ps and 16.6 ps is obtained, respectively. In connection with standard PC hardware, the system allows long-term acquisition and storage of measurement data over several weeks. A comparison is given to the Dual Mixer Time Difference (DMTD) and Time Interval Counter (TIC), which are state-of-the-art measurement methods for sine and pulse signal analysis, respectively. Furthermore, we show that our proposed USRP-based approach outperforms measurements with a high-grade Digital Sampling Oscilloscope.Comment: 10 pages, 15 figures, and 4 table

Design And Implementation Of Low Passband Ripple Digital Down Converter Filter For Software Defined Radio Transceiver

The main aim of this research is the design and implementation of the Digital Down Converter (DDC) filter with low passband ripple and high attenuation in the adjacent rejection and blocker requirements in the filter response for Software Defined Radio (SDR) transceiver to decrease the power consumption and avoid the interference in the channel. The proposed DDC filters incorporate of Remez algorithm and Mini-max algorithm to reduce the error rate in the filter response. The DDC filter is acombination of 5-stages Cascaded Integrated Comb (CIC) filter and two linear phase Equiripple FIR filter (CFIR and PFIR). The passband ripple, adjacent rejection and blocker band is developed by controlling the transition width, filter order and weight function of the FIR filter using MATLAB and Xilinx System Generator environment

Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

Low power, reduced complexity filtering and improved tracking accuracy for GNSS

This thesis addresses the power consumption problems resulting from the advent of multiple GNSS satellite systems which create the need for receivers supporting multi-frequency, multi-constellation GNSS systems. Such a multi-mode receiver requires a substantial amount of signal processing power which translates to increased hardware complexity and higher power dissipation which reduces the battery life of a mobile platform. During the course of the work undertaken, a power analysis tool was developed in order to be able to estimate the hardware utilisation as well as the power consumption of a digital system. By using the power estimation tool developed, it was established that most of the power was dissipated after the Analog to Digital Converter (ADC)by the filters associated with the decimation process. The power dissipation and the hardware complexity of the decimator can be reduced substantially by using a minimum-phase Infinite Impulse Response (IIR) filter. For Global Positioning System (GPS) civilian signals, the use of IIR filters does not deleteriously affect the positional accuracy. However, in the case where an IIR filter was deployed in a GLObalnaya NAvigatsionnaya Sputnikovaya Sistema (GLONASS) receiver, the pseudorange measurements of the receiver varied by up to 200 metres. The work undertaken proposes various methods that overcomes the pseudorange measurement variation and reports on the results that are on par with linear-phase Finite Impulse Response (FIR) filters. The work also proposes a modified tracking loop that is capable of tracking very low Doppler frequencies without decreasing the tracking performance