ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency

Research and development of diagnostic algorithms to support fault accommodating control for emerging shipboard power system architectures

The U.S. Navy has proposed development of next generation warships utilising an increased amount of power electronics devices to improve flexibility and controllability. The high power density finite inertia network is envisioned to employ automated fault detection and diagnosis to aid timely remedial action. Integration of condition monitoring and fault diagnosis to form an intelligent power distribution system is anticipated to assist decision support for crew while enhancing security and mission availability. This broad research being in the conceptual stage has lack of benchmark systems to learn from. Thorough studies are required to successfully enable realising benefits offered by using increased power electronics and automation. Application of fundamental analysis techniques is necessary to meticulously understand dynamics of a novel system and familiarisation with associated risks and their effects. Additionally, it is vital to find ways of mitigating effects of identified risks. This thesis details the developing of a generalised methodology to help focus research into artificial intelligence (AI) based diagnostic techniques. Failure Mode and Effects Analysis (FMEA) is used in identifying critical parts of the architecture. Sneak Circuit Analysis (SCA) is modified to provide signals that differentiate faults at a component level of a dc-dc step down converter. These reliability analysis techniques combined with an appropriate AI-algorithm offer a potentially robust approach that can potentially be utilised for diagnosing faults within power electronic equipment anticipated to be used onboard the novel SPS. The proposed systematic methodology could be extended to other types of power electronic converters, as well as distinguishing subsystem level faults. The combination of FMEA, SCA with AI could also be used for providing enhanced decision support. This forms part of future research in this specific arena demonstrating the positives brought about by combining reliability analyses techniques with AI for next generation naval SPS.The U.S. Navy has proposed development of next generation warships utilising an increased amount of power electronics devices to improve flexibility and controllability. The high power density finite inertia network is envisioned to employ automated fault detection and diagnosis to aid timely remedial action. Integration of condition monitoring and fault diagnosis to form an intelligent power distribution system is anticipated to assist decision support for crew while enhancing security and mission availability. This broad research being in the conceptual stage has lack of benchmark systems to learn from. Thorough studies are required to successfully enable realising benefits offered by using increased power electronics and automation. Application of fundamental analysis techniques is necessary to meticulously understand dynamics of a novel system and familiarisation with associated risks and their effects. Additionally, it is vital to find ways of mitigating effects of identified risks. This thesis details the developing of a generalised methodology to help focus research into artificial intelligence (AI) based diagnostic techniques. Failure Mode and Effects Analysis (FMEA) is used in identifying critical parts of the architecture. Sneak Circuit Analysis (SCA) is modified to provide signals that differentiate faults at a component level of a dc-dc step down converter. These reliability analysis techniques combined with an appropriate AI-algorithm offer a potentially robust approach that can potentially be utilised for diagnosing faults within power electronic equipment anticipated to be used onboard the novel SPS. The proposed systematic methodology could be extended to other types of power electronic converters, as well as distinguishing subsystem level faults. The combination of FMEA, SCA with AI could also be used for providing enhanced decision support. This forms part of future research in this specific arena demonstrating the positives brought about by combining reliability analyses techniques with AI for next generation naval SPS

Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers

Proper short-circuit protection in dc distribution systems has provided an austere challenge to researchers as the development of commercially-viable equipment providing fast operation, coordination and reliability still continues. The objective of this thesis is to analyze issues associated with short-circuit protection of low-voltage dc (LVDC) distribution systems and propose a short-circuit protection methodology based on solid-state circuit breakers (SSCBs) that provides fault-current limiting (FCL). Simulation results for a simplified notional 1-kVdc distribution system, performed in MATLAB/SIMULINKTM, would be presented to illustrate that SSCB solutions based on reverse-blocking integrated gate-commutated thyristors (RB-IGCT) are feasible for low-voltage dc distribution systems but requires connecting several devices in parallel to open fast-rising fault currents. To validate the implementation of the FCL function, the coordination between upstream and downstream SSCBs during a fault at different operating conditions of the system is presented. In addition, several fault-detection techniques would be compared by means of the let-through energies, and the impact of FCL on the thermal handling requirements of the RB-IGCT would also be discussed

Comparative Analysis of Different Control Schemes for DC-DC Converter: a Review

DC-DC converters are some power electronic circuits that convert the DC voltage from one level to another. They have a very large area of applications ranging from computing to communication. They are widely used in appliance control transportations and high-power transmission. Its increasing demand is based on its capability of electrical energy conversion. The basic topologies of DC-DC converter are Buck converter and Boost converter, other topologies are derived from these two basic topologies. Mathematical modelling of both Buck converters is done. Some of the control schemes are summarized in this paper. Current mode control (CMC), PID, Sliding Mode (SM) control including their advantages and disadvantages are highlighted in this paper

Low Voltage Regulator Modules and Single Stage Front-end Converters

Evolution in microprocessor technology poses new challenges for supplying power to these devices. To meet demands for faster and more efficient data processing, modem microprocessors are being designed with lower voltage implementations. More devices will be packed on a single processor chip and the processors will operate at higher frequencies, exceeding 1GHz. New high-performance microprocessors may require from 40 to 80 watts of power for the CPU alone. Load current must be supplied with up to 30A/µs slew rate while keeping the output voltage within tight regulation and response time tolerances. Therefore, special power supplies and Voltage Regulator Modules (VRMs) are needed to provide lower voltage with higher current and fast response. In the part one (chapter 2,3,4) of this dissertation, several low-voltage high-current VRM technologies are proposed for future generation microprocessors and ICs. The developed VRMs with these new technologies have advantages over conventional ones in terms of efficiency, transient response and cost. In most cases, the VRMs draw currents from DC bus for which front-end converters are used as a DC source. As the use of AC/DC frond-end converters continues to increase, more distorted mains current is drawn from the line, resulting in lower power factor and high total harmonic distortion. As a branch of active Power factor correction (PFC) techniques, the single-stage technique receives particular attention because of its low cost implementation. Moreover, with continuously demands for even higher power density, switching mode power supply operating at high-frequency is required because at high switching frequency, the size and weight of circuit components can be remarkably reduced. To boost the switching frequency, the soft-switching technique was introduced to alleviate the switching losses. The part two (chapter 5,6) of the dissertation presents several topologies for this front-end application. The design considerations, simulation results and experimental verification are discussed

DC-DC power converter research for Orbiter/Station power exchange

This project was to produce innovative DC-DC power converter concepts which are appropriate for the power exchange between the Orbiter and the Space Station Freedom (SSF). The new converters must interface three regulated power buses on SSF, which are at different voltages, with three fuel cell power buses on the Orbiter which can be at different voltages and should be tracked independently. Power exchange is to be bi-directional between the SSF and the Orbiter. The new converters must satisfy the above operational requirements with better weight, volume, efficiency, and reliability than is available from the present conventional technology. Two families of zero current DC-DC converters were developed and successfully adapted to this application. Most of the converters developed are new and are presented

High Performance Low Voltage Power Mosfet For High-frequency Synchronous Buck Converters

Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with iv its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35µm process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power v Block incorporating these new device techniques is demonstrated with an excellent efficiency observed

Review of Electric Vehicle Charging Technologies, Configurations, and Architectures

Electric Vehicles (EVs) are projected to be one of the major contributors to energy transition in the global transportation due to their rapid expansion. The EVs will play a vital role in achieving a sustainable transportation system by reducing fossil fuel dependency and greenhouse gas (GHG) emissions. However, high level of EVs integration into the distribution grid has introduced many challenges for the power grid operation, safety, and network planning due to the increase in load demand, power quality impacts and power losses. An increasing fleet of electric mobility requires the advanced charging systems to enhance charging efficiency and utility grid support. Innovative EV charging technologies are obtaining much attention in recent research studies aimed at strengthening EV adoption while providing ancillary services. Therefore, analysis of the status of EV charging technologies is significant to accelerate EV adoption with advanced control strategies to discover a remedial solution for negative grid impacts, enhance desired charging efficiency and grid support. This paper presents a comprehensive review of the current deployment of EV charging systems, international standards, charging configurations, EV battery technologies, architecture of EV charging stations, and emerging technical challenges. The charging systems require a dedicated converter topology, a control strategy and international standards for charging and grid interconnection to ensure optimum operation and enhance grid support. An overview of different charging systems in terms of onboard and off-board chargers, AC-DC and DC-DC converter topologies, and AC and DC-based charging station architectures are evaluated

Modular Hybrid Energy Concept Employing a Novel Control Structure Based on a Simple Analog System

This paper proposes a novel control topology which enables the setup of a low cost analog system leading to the implementation of a modular energy conversion system. The modular concept is based on hybrid renewable energy (solar and wind) and uses high voltage inverters already available on the market. An important feature of the proposed topology is a permanently active current loop, which assures short circuit protection and simplifies the control loops compensation. The innovative analogue solution of the control structure is based on a dedicated integrated circuit (IC) for power factor correction (PFC) circuits, used in a new configuration, to assure an efficient inverter start-up. The energy conversion system (control structure and maximum power point tracking algorithm) is simulated using a new macromodel-based concept, which reduces the usual computational burden of the simulator and achieves high processing speed. The proposed novel system is presented in this article from concept, through the design and implementation stages, is verified through simulation and is validated by experimental results