Implementing video compression algorithms on reconfigurable devices

The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete system and the power consumption of FPGA based video encoders. Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to improve the efficiency with which input video sequences can be loaded over the system bus. The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder

A flexible heterogeneous hardware/software solution for real-time high-definition H.264 motion estimation

International audienceThe MPEG-4 AVC/H.264 video compression standard introduces a high degree of motion estimation complexity. Quarter-pixel accuracy and variable block-size significantly enhance compression performances over previous standards, but increase computation requirements. Firstly, a DSP-based solution achieves real-time integer motion estimation. Nevertheless, fractional-pixel refinement is too computationally intensive to be efficiently processed on a software-based processor. Secondly, to address this restriction, a flexible and low complexity VLSI sub-pixel refinement coprocessor is designed. Thanks to an improved datapath, a high throughput is achieved with low logic resources. Finally, we propose a heterogeneous (DSP-FPGA) solution to handle real-time motion estimation with variable block-size and fractional-pixel accuracy for high-definition video. It combines efficiency and programmability. The flexibility offers complexity versus performance trade-offs. The system achieves motion estimation of 720p sequences at up to 60 frames per second

Low Complexity Interpolation Filters for Motion Estimation and Application to the H.264 Encoders

Techniques for image super-resolution play an important role in a plethora of applications, which include video compression and motion estimation. The detection of the fractional displacements among frames facilitates the removal of temporal redundancy and improves the video quality by 2-4 dB PSNR. However, the increased complexity of the Fractional Motion Estimation (FME) process adds a significant computational load to the encoder and sets constraints to real-time designs. Researchers have performed timing analysis for the motion estimation process and they reported that FME accounts for almost half of the entire motion estimation period, which in turn accounts for 60-90% of the total encoding time depending on the design configuration

High Speed Dim Air Target Detection Using Airborne Radar under Clutter and Jamming Effects

The challenging potential problems associated with using airborne radar in detection of high Speed Maneuvering Dim Target (HSMDT) are the highly noise, jamming and clutter effects. The problem is not only how to remove clutter and jamming as well as the range migration and Doppler ambiguity estimation problems due to high relative speed between the targets and airborne radar. Some of the recently published works ignored the range migration problems, while the others ignored the Doppler ambiguity estimation. In this paper a new hybrid technique using Optimum Space Time Adaptive Processing (OSTAP), Second Order Keystone Transform (SOKT), and the Improved Fractional Radon Transform (IFrRT) was proposed. The OSTAP was applied as anti-jamming and clutter rejection method, the SOKT corrects the range curvature and part of the range walk, then the IFrRT estimates the target’ radial acceleration and corrects the residual range walk. The simulation demonstrates the validity and effectiveness of the proposed technique, and its advantages over the previous researches by comparing its probability of detection with the traditional methods. The new approach increases the probability of detection, and also overcomes the limitation of Doppler frequency ambiguity

Novel VLSI architecture of motion estimation and compensation for H.264 standard

This thesis presents a high performance novel VLSI architecture of a H.264 motion estimator, which can be used as a building block for real-time H.264 video compression. Full-search block matching algorithm was used in this design. Pipeline structure was developed for variable block size processing units to work in parallel. The speed at 125MHz is good for real time motion estimation with 25/sec frame rate and 640x480 resolutions. The processing speed is also independent of the threshold level of Sum of Absolute Difference (SAD), which is used to determine the size of the macro block. The architecture is implemented with Register Transfer Level VHDL codes then synthesized with Synopsys Design Compiler, using TSMC 0.25um technology. The synthesized Application Specific Integrated Circuits (ASIC\u27s) has an area of 664um x 664um

Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard

This paper focuses on motion estimation engine design in future high-efficiency video coding (HEVC) encoders. First, a methodology is explained to analyze hardware implementation cost in terms of hardware area, memory size and memory bandwidth for various possible motion estimation engine designs. For 11 different configurations, hardware cost as well as the coding efficiency are quantified and are compared through a graphical analysis to make design decisions. It has been shown that using smaller block sizes (e.g. 4 × 4) imposes significantly larger hardware requirements at the expense of modest improvements in coding efficiency. Secondly, based on the analysis on various configurations, one configuration is chosen and algorithm improvements are presented to further reduce hardware implementation cost of the selected configuration. Overall, the proposed changes provide 56 × on-chip bandwidth, 151 × off-chip bandwidth, 4.3 × core area and 4.5 × on-chip memory area savings when compared to the hardware implementation of the HM-3.0 design.Texas Instruments Incorporate