Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Nonlinear models and algorithms for RF systems digital calibration

Focusing on the receiving side of a communication system, the current trend in pushing the digital domain ever more closer to the antenna sets heavy constraints on the accuracy and linearity of the analog front-end and the conversion devices. Moreover, mixed-signal implementations of Systems-on-Chip using nanoscale CMOS processes result in an overall poorer analog performance and a reduced yield. To cope with the impairments of the low performance analog section in this "dirty RF" scenario, two solutions exist: designing more complex analog processing architectures or to identify the errors and correct them in the digital domain using DSP algorithms. In the latter, constraints in the analog circuits' precision can be offloaded to a digital signal processor. This thesis aims at the development of a methodology for the analysis, the modeling and the compensation of the analog impairments arising in different stages of a receiving chain using digital calibration techniques. Both single and multiple channel architectures are addressed exploiting the capability of the calibration algorithm to homogenize all the channels' responses of a multi-channel system in addition to the compensation of nonlinearities in each response. The systems targeted for the application of digital post compensation are a pipeline ADC, a digital-IF sub-sampling receiver and a 4-channel TI-ADC. The research focuses on post distortion methods using nonlinear dynamic models to approximate the post-inverse of the nonlinear system and to correct the distortions arising from static and dynamic errors. Volterra model is used due to its general approximation capabilities for the compensation of nonlinear systems with memory. Digital calibration is applied to a Sample and Hold and to a pipeline ADC simulated in the 45nm process, demonstrating high linearity improvement even with incomplete settling errors enabling the use of faster clock speeds. An extended model based on the baseband Volterra series is proposed and applied to the compensation of a digital-IF sub-sampling receiver. This architecture envisages frequency selectivity carried out at IF by an active band-pass CMOS filter causing in-band and out-of-band nonlinear distortions. The improved performance of the proposed model is demonstrated with circuital simulations of a 10th-order band pass filter, realized using a five-stage Gm-C Biquad cascade, and validated using out-of-sample sinusoidal and QAM signals. The same technique is extended to an array receiver with mismatched channels' responses showing that digital calibration can compensate the loss of directivity and enhance the overall system SFDR. An iterative backward pruning is applied to the Volterra models showing that complexity can be reduced without impacting linearity, obtaining state-of-the-art accuracy/complexity performance. Calibration of Time-Interleaved ADCs, widely used in RF-to-digital wideband receivers, is carried out developing ad hoc models because the steep discontinuities generated by the imperfect canceling of aliasing would require a huge number of terms in a polynomial approximation. A closed-form solution is derived for a 4-channel TI-ADC affected by gain errors and timing skews solving the perfect reconstruction equations. A background calibration technique is presented based on cyclo-stationary filter banks architecture. Convergence speed and accuracy of the recursive algorithm are discussed and complexity reduction techniques are applied

Etude et conception d'algorithmes de correction d'erreurs dans des structures de conversion analogique-numérique entrelacées pour applications radar et guerre électronique

The evolution of radar and electronic warfare systems tends to develop digitalreceivers with wider bandwidths. This constraint reaches the Analog to Digital Converters(ADC) which must provide a sample rate higher and higher while maintaining a reducedpower dissipation. A solution to meet this demand is the Time-Interleaved ADC (TIADC)which parallelizes M ADCs, increasing the sampling frequency of an M factor while still ina proportionate relation to the power loss. However, the dynamic performance of TIADCsare reduced by errors related to the mismatches between the sampling channels, due to themanufacturing processes, the supply voltage and the temperature variations. These errors canbe modeled as the result of offset, gain and clock-skew mismatches and globally as from thefrequency response mismatches. It is these last mismatches, unless addressed in the literaturethat carry our work. The objective is to study these errors to derive a model and an estimationmethod then, to propose digital compensation methods that can be implemented on a FPGAtarget.First, we propose a general TIADC model using frequency response mismatches for any Mchannel number. Our model merge a continuous-time description of mismatches and a discretetimeone of the interleaving process, resulting in an expression of the TIADC errors as a linearperiodic time-varying (LPTV) system applied to the uniformly sampled analog signal. Then,we propose a method to estimate TIADC errors based on the correlation properties of theoutput signal for any M channel. Next, we define a frequency response mismatch compensationarchitecture for TIADC errors and we study its performance related to its configuration and theinput signal. We describe an FPGA implementation of this architecture for M=4 interleavedchannels and we study the resources consumption to propose optimisations. Finally, we proposea second compensation method, specific to M=2 interleaved channels and derived from the firstone, but working on the analytical signal from the TIADC output and we compare it to a similarstate-of-the-art method.L’ évolution des systèmes radar et de guerre électronique tend à concevoir desrécepteurs numériques possédant des bandes instantanées de plus en plus larges. Cette contraintese reporte sur les Convertisseurs Analogique-Numérique (CAN) qui doivent fournir une fréquenced’échantillonnage de plus en plus élevée tout en conservant une puissance dissipée réduite. Unesolution pour répondre à cette demande est le CAN à Temps Entrelacés (ET-CAN) qui paralléliseM CANs pour augmenter la fréquence d’échantillonnage d’un facteur M tout en restant dansun rapport proportionné avec la puissance dissipée. Cependant, les performances dynamiquesdes ET-CANs sont réduites par des défauts d’entrelacements liés à des différences de processusde fabrication, de leur tension d’alimentation et des variations de température. Ces défautspeuvent être modélisés comme issus des disparités d’offsets, de gains ou décalages temporels etglobalement comme issus des disparités de réponses fréquentielles. Ce sont sur ces dernièresdisparités, moins traitées dans la littérature, que portent nos travaux. L’objectif est d’étudierces disparités pour en déduire un modèle et une méthode d’estimation puis, de proposer desméthodes de compensation numérique qui peuvent être implémentées sur une cible FPGA.Pour cela, nous proposons un modèle général des disparités de réponses fréquentielles desET-CANs pour un nombre de voies M quelconques. Celui-ci mélange une description continuedes disparités et une description discrète de l’entrelacement, résultant sur une expression desdéfauts des ET-CANs comme un filtrage à temps variant périodique (LPTV) du signal analogiqueéchantillonné uniformément. Puis, nous proposons une méthode d’estimation des disparitésdes ET-CANs basée sur les propriétés de corrélation du signal en sortie du modèle, pour Mvoies quelconques. Ensuite, nous définissions une architecture de compensation des disparitésde réponses fréquentielles des ET-CANs et nous étudions ses performances en fonction de sesconfigurations et du signal en entrée. Nous décrivons une implémentation de cette architecturepour M=4 voies entrelacées sur cible FPGA et nous étudions les ressources consommées afin deproposer des pistes d’optimisation. Enfin, nous proposons une seconde méthode de compensationspécifique au cas M=2 voies entrelacées, dérivée de la première mais travaillant sur le signalanalytique en sortie d’un ET-CAN et nous la comparons à une méthode similaire de l’état del’art

Tecnologias coerentes para redes ópticas flexíveis

Next-generation networks enable a broad range of innovative services with the best delivery by utilizing very dense wired/wireless networks. However, the development of future networks will require several breakthroughs in optical networks such as high-performance optical transceivers to support a very-high capacity optical network as well as optimization of the network concept, ensuring a dramatic reduction of the cost per bit. At the same time, all of the optical network segments (metro, access, long-haul) need new technology options to support high capacity, spectral efficiency and data-rate flexibility. Coherent detection offers an opportunity by providing very high sensitivity and supporting high spectral efficiency. Coherent technology can still be combined with polarization multiplexing. Despite the increased cost and complexity, the migration to dual-polarization coherent transceivers must be considered, as it enables to double the spectral efficiency. These dual-polarization systems require an additional digital signal processing (DSP) subsystem for polarization demultiplexing. This work seeks to provide and characterize cost-effective novel coherent transceivers for the development of new generation practical, flexible and high capacity transceivers for optical metro-access and data center interconnects. In this regard, different polarization demultiplexing (PolDemux) algorithms, as well as adaptive Stokes will be considered. Furthermore, low complexity and modulation format-agnostic DSP techniques based on adaptive Stokes PolDemux for flexible and customizable optical coherent systems will be proposed. On this subject, the performance of the adaptive Stokes algorithm in an ultra-dense wavelength division multiplexing (U-DWDM) system will be experimentally evaluated, in offline and real-time operations over a hybrid optical-wireless link. In addition, the efficiency of this PolDemux algorithm in a flexible optical metro link based on Nyquist pulse shaping U-DWDM system and hybrid optical signals will be assessed. Moreover, it is of great importance to find a transmission technology that enables to apply the Stokes PolDemux for long-haul transmission systems and data center interconnects. In this work, it is also proposed a solution based on the use of digital multi-subcarrier multiplexing, which improve the performance of long-haul optical systems, without increasing substantially, their complexity and cost.As redes de telecomunicações futuras permitirão uma ampla gama de serviços inovadores e com melhor desempenho. No entanto, o desenvolvimento das futuras redes implicará vários avanços nas redes de fibra ótica, como transcetores óticos de alto desempenho capazes de suportar ligações de muito elevada capacidade, e a otimização da estrutura da rede, permitindo uma redução drástica do custo por bit transportado. Simultaneamente, todos os segmentos de rede ótica (metropolitanas, acesso e longo alcance) necessitam de novas opções tecnológicas para suportar uma maior capacidade, maior eficiência espetral e flexibilidade. Neste contexto, a deteção coerente surge como uma oportunidade, fornecendo alta sensibilidade e elevada eficiência espetral. A tecnologia de deteção coerente pode ainda ser associada à multiplexação na polarização. Apesar de um potencial aumento ao nível do custo e da complexidade, a migração para transcetores coerentes de dupla polarização deve ser ponderada, pois permite duplicar a eficiência espetral. Esses sistemas de dupla polarização requerem um subsistema de processamento digital de sinal (DSP) adicional para desmultiplexagem da polarização. Este trabalho procura fornecer e caracterizar novos transcetores coerentes de baixo custo para o desenvolvimento de uma nova geração de transcetores mais práticos, flexíveis e de elevada capacidade, para interconexões óticas ao nível das futuras redes de acesso e metro. Assim, serão analisados diferentes algoritmos para a desmultiplexagem da polarização, incluindo uma abordagem adaptativa baseada no espaço de Stokes. Além disso, são propostas técnicas de DSP independentes do formato de modulação e de baixa complexidade baseadas na desmultiplexagem de Stokes adaptativa para sistemas óticos coerentes flexíveis. Neste contexto, o desempenho do algoritmo adaptativo de desmultiplexagem na polarização baseado no espaço de Stokes é avaliado experimentalmente num sistema U-DWDM, tanto em análises off-line como em tempo real, considerando um percurso ótico hibrido que combina um sistema de transmissão suportado por fibra e outro em espaço livre. Foi ainda analisada a eficiência do algoritmo de desmultiplexagem na polarização numa rede ótica de acesso flexível U-DWDM com formatação de pulso do tipo Nyquist. Neste trabalho foi ainda analisada a aplicação da técnica de desmultiplexagem na polarização baseada no espaço de Stokes para sistemas de longo alcance. Assim, foi proposta uma solução de aplicação baseada no uso da multiplexagem digital de múltiplas sub-portadoras, tendo-se demonstrado uma melhoria na eficiência do desempenho dos sistemas óticos de longo alcance, sem aumentar significativamente a respetiva complexidade e custo.Programa Doutoral em Engenharia Eletrotécnic

Analysis and design of low-power data converters

In a large number of applications the signal processing is done exploiting both analog and digital signal processing techniques. In the past digital and analog circuits were made on separate chip in order to limit the interference and other side effects, but the actual trend is to realize the whole elaboration chain on a single System on Chip (SoC). This choice is driven by different reasons such as the reduction of power consumption, less silicon area occupation on the chip and also reliability and repeatability. Commonly a large area in a SoC is occupied by digital circuits, then, usually a CMOS short-channel technological processes optimized to realize digital circuits is chosen to maximize the performance of the Digital Signal Proccessor (DSP). Opposite, the short-channel technology nodes do not represent the best choice for analog circuits. But in a large number of applications, the signals which are treated have analog nature (microphone, speaker, antenna, accelerometers, biopotential, etc.), then the input and output interfaces of the processing chip are analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC) both digital and analog circuits can be found. This gives advantages in term of total size, cost and power consumption of the SoC. The specific characteristics of CMOS short-channel processes such as: • Low breakdown voltage (BV) gives a power supply limit (about 1.2 V). • High threshold voltage VTH (compared with the available voltage supply) fixed in order to limit the leakage power consumption in digital applications (of the order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many problems with the stacked topologies. • Threshold voltage dependent on the channel length VTH = f(L) (short channel effects). • Low value of the output resistance of the MOS (r0) and gm limited by speed saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20 to 26dB. • Mismatch which brings offset effects on analog circuits. make the design of high performance analog circuits very difficult. Realizing lowpower circuits is fundamental in different contexts, and for different reasons: lowering the power dissipation gives the capability to reduce the batteries size in mobile devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the life of remote sensing devices, satellites, space probes, also allows the reduction of the size and weight of the heat sink. The reduction of power dissipation allows the realization of implantable biomedical devices that do not damage biological tissue. For this reason, the analysis and design of low power and high precision analog circuits is important in order to obtain high performance in technological processes that are not optimized for such applications. Different ways can be taken to reduce the effect of the problems related to the technology: • Circuital level: a circuit-level intervention is possible to solve a specific problem of the circuit (i.e. Techniques for bandwidth expansion, increase the gain, power reduction, etc.). • Digital calibration: it is the highest level to intervene, and generally going to correct the non-ideal structure through a digital processing, these aims are based on models of specific errors of the structure. • Definition of new paradigms. This work has focused the attention on a very useful mixed-signal circuit: the pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in high-precision applications where a resolution of about 10-16 bits and sampling rates above hundreds of Mega-samples per second (telecommunication, radar, etc.) are needed. An introduction on the theory of pipeline ADC, its state of the art and the principal non-idealities that affect the energy efficiency and the accuracy of this kind of data converters are reported in Chapter 1. Special consideration is put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep submicron technology nodes side effects called short channel effects exist opposed to older technology nodes where undesired effects are not present. An overview of the short channel effects and their consequences on design, and also power consuption reduction techniques, with particular emphasis on the specific techniques adopted in pipelined ADC are reported in Chapter 2. Moreover, another way may be undertaken to increase the accuracy and the efficiency of an ADC, this way is the digital calibration. In Chapter 3 an overview on digital calibration techniques, and furthermore a new calibration technique based on Volterra kernels are reported. In some specific applications, such as software defined radios or micropower sensor, some circuits should be reconfigurable to be suitable for different radio standard or process signals with different charateristics. One of this building blocks is the ADC that should be able to reconfigure the resolution and conversion frequency. A reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply starting from the required conversion frequency was developed, and the results are reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for the feedback loop and its theory is described

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities