높은 구동 전류와 낮은 문턱전압 이하 스윙을 가지는 L자 형태의 터널링 전계효과 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 박병국.In order to solve power crisis in highly-scaled CMOS technology, a novel tunnel field-effect transistors (TFETs), named L-shaped TFETs, have been proposed and its electrical properties are examined. It features band-to-band tunneling (BTBT) direction parallel to the normal electric field induced by gate electrode. Because carrier injection is occurred perpendicular to the channel direction, cross-sectional area and barrier width of BTBT junction could be defined by structural parameters. Using the commercial TCAD device simulator, its electrical characteristics are examined and optimized. It is expected that the L-shaped TFETs will reveal better performance than conventional ones in terms of subthreshold swing (S), on-current (Ion) and short channel effect. In addition, the performance of L-shaped TFET inverters has been compared with that of conventional TFET ones for its complementary logic application. After the key process techniques are obtained, control and comparison samples are fabricated at Inter-University Semiconductor Research Center (ISRC) of Seoul National University (SNU), Korea. The main process technique is as follow: in-situ doped epitaxial layer growth for constantly doped source region, selective epitaxial layer growth of silicon at low temperature for tunneling region, and guarantee sub-3-nm gate dielectric. From the electrical measurement of transfer and output characteristics, it is verified that 102 mV/dec minimum S in conventional TFET is improve to 7, 34 and 59 mV/dec in L-shaped TFET. In addition, the Ion of L-shaped TFET is more than 10 times larger than that of conventional one. Extracting several parameters such as source/drain resistance, channel resistance, mobility, and tunneling resistance, it is clear that the improved performance comes from the reduction of tunneling resistance. From this study, it is demonstrated that L-shaped TFET will be one of the most promising candidate for a next-generation low-power device.Abstract i Contents iii List of Tables v List of Figures vi Chapter 1 Introduction 1 1.1 NECESSITY OF ALTERNATIVES TO CMOS 1 1.2 TUNNEL FIELD-EFFECT TRANSISTORS (TFETS) 4 1.3 TECHNICAL ISSUES OF TFETS 7 1.4 SCOPE OF THESIS 10 Chapter 2 L-shaped TFET 11 2.1 FEATURES OF L-SHAPED TFET 11 2.2 DESIGN OPTIMIZATION 17 2.3 CORNER EFFECT 27 2.4 FURTHER IMPROVEMENT AND CIRCUIT APPLICATION 36 2.5 SUMMARY OF TARGET DEVICE 40 Chapter 3 Device Fabrication 42 3.1 FABRICATION OF CONTROL TFETS 42 3.2 KEY PROCESS DESIGNS FOR L-SHAPED TFETS 45 3.3 FABRICATION OF L-SHAPED TFET 51 3.4 SIDEWALL SPACER FOR MINIMIZATION OF MIS-ALIGNMENT 56 Chapter 4 Device Characteristics 59 4.1 METAL-OXIDE-SEMICONDUCTOR (MOS) CAPACITOR 59 4.2 CONTROL SAMPLES OF CONVENTIONAL PLANAR TFETS 63 4.3 L-SHAPED TFETS 71 4.4 EXTRACTION OF SEVERAL ELECTRICAL PARAMETERS 76 Chapter 5 80 Conclusions 80 Bibliography 82 Abstract in Korean 89 Curriculum Vitae 91Docto

높은 전류구동능력을 위한 Si/SiGe 물질을 가지는 터널링 전계효과 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 박병국.For integrated circuits with highly-scaled complementary MOS (CMOS) technology, power dissipation problem has become an important issue since power per chip continues to increases and leakage power dominates in advanced technology nodes. In order to solve power issues, the supply voltage (VDD) scaling is very essential and devices which have low leakage current are needed. Recently, many research groups have studied a tunnel field-effect transistors (tunnel FETs) which is suitable for low operating power device. Tunnel FETs have very low leakage current and small subthrehold swing (SS) at room temperature unlike CMOS because of carrier injection using tunneling. In this thesis, a novel tunnel FET with SiGe body and elevated Si drain region have been proposed. The proposed tunnel FET has larger current drivability than conventional Si tunnel FETs because it uses a narrow bandgap material for low tunneling resistance. Also, it is expected that electrical characteristics can be improved by using SiGe channel and source for n-channel as well as p-channel operation. In addition, ambipolar current that is caused by band-to-band tunneling (BTBT) between channel and drain can be suppressed by using elevated Si drain region. For obtaining fundamental electrical properties of tunnel FET with SiGe body, planar structures are firstly fabricated and analyzed with Si tunnel FET. From electrical characteristics of fabricated devices, it is observed that both n-type and p-type SiGe tunnel FETs have better switching properties than Si devices. Current saturations become faster and drive current shows 10 times more than that of Si tunnel FETs. In addition, BTBT model parameters of Si and Ge materials in fabricated devices are extracted through TCAD simulation. Extracted A and B parameters of BTBT model in Si are 4×1014 cm-1s-1 and 9.9×106 V/cm. Also, A and B parameters of Ge can be extracted as 3.1×1016 cm-1s-1 and 7.1×105 V/cm, respectively. Using calibrated model parameters, proposed tunnel FET is simulated and optimized in terms of switching properties with changing Ge contents, effect of the elevated Si drain region, short-channel effects, inverter operation, and device delay. Based on these optimized simulation results, the proposed tunnel FET is fabricated using spacer technique because it is possible to make self-aligned doping process. Key unit process is as follows: epitaxial growth for Si and SiGe materials, e-beam lithography for active-fin formation, and sidewall spacer gate formation. For n-channel and p-channel operation, fabricated tunnel FET shows the better electrical characteristics than control groups. Extracted point SS is 51.1 mV/dec for p-type tunnel FET and 87 mV/dec for n-type tunnel FET. Ambipolar current of the proposed tunnel FET is suppressed to 1/100 of that of planar SiGe tunnel FET. Also, in order to analyze current flow mechanism of tunnel FET, the electrical characteristics are measured with temperature variation. As temperature goes up, Shockley-Read-Hall and field-dependent generation are increased resulting in degradation of switching property. In current saturation region, BTBT which has low temperature sensitivity is dominant on current property. From this study, it is demonstrated that the novel tunnel FET with SiGe body and the elevated Si drain shows improved electrical performance compared with Si tunnel FET. Also, both n-type and p-type devices can obtain high current drivability and small SS without structure changes. This means that the proposed device has strong advantage in terms of implementing IC with tunnel FET. Thus, it will be one of the promising candidates for next-generation devices.Abstract i Contents iv List of Figures vi Chapter 1 1 Introduction 1 1.1 POWER ISSUES ON CMOS TECHNOLOGIES 1 1.2 TUNNEL FIELD-EFFECT TRANSISTOR (TUNNEL FET) 3 1.3 ISSUES IN TUNNEL FET 6 1.4 SCOPE OF THESIS 9 Chapter 2 11 Planar Si and SiGe tunnel FETs 11 2.1 EXPITAXY GROWTH FOR SI AND SIGE LAYERS 11 2.2 SIGE MOSCAP AND MOSFET FABRICATION 14 2.3 PLANAR SI AND SIGE TUNNEL FET 15 2.4 SUMMARY 34 Chapter 3 35 Device Simulation 35 3.1 PROPOSED TUNNEL FET 35 3.2 SIMULATION PARAMETERS AND RESULTS 37 3.3 TRANSIENT RESPONSE CHARACTERISTICS 43 Chapter 4 51 Device Characteristics 51 4.1 PROCESS FLOW 51 4.2 ACTIVE FIN PATTERNING USING E-BEAM LITHOGRAPHY 54 4.3 DRAIN AND GATE FORMATION 56 4.4 DEVICE CHARACTERISTICS 61 4.5 REASON OF DEGRADED CHARACTERISTICS IN N-TYPE DEVICE 70 Chapter 5 73 Conclusions 73 Bibliography 77 초록 78Docto

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

질화갈륨 발광다이오드의 내부 양자 효율에 대한 분석 및 향상

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 박병국.In order to extract the recombination coefficient and the internal quantum efficiency (IQE) of the GaN-based LEDs, a fast and reliable measurement method using transient characteristics is developed. For accurate extraction of the recombination coefficients and the IQE, an improved rate equation model for GaN-based LEDs considering the effective volume of the active region is also proposed. Through TCAD simulations, it is confirmed that the IQE, especially efficiency droop is related with small effective volume. Also, it is confirmed that the effective volume is controlled by polarization charge, the barriers between the quantum wells, and current density. The trap and its impact on the GaN-based LEDs are also analyzed by measurement and TCAD simulation. A reversible increase in the current of GaN-based blue LEDs is observed when constant forward voltage is applied. This characteristic is assumed to be the result of trapping process, and a trap activation energy of 0.30 eV is extracted. Through TCAD simulations, it is confirmed that the multi-quantum well (MQW) barrier height is reduced by the hole trapping process and that the current is increased by lowering this barrier. It is also confirmed that the effect of this trap on the optical characteristics of GaN-based blue LEDs by TCAD simulation and measurement. To improve the IQE of GaN-based LEDs, a novel structure for GaN-based LED featuring p-type trench in the MQW is proposed. Through TCAD simulation, it is confirmed that the proposed structure shows quite uniform hole distribution in the MQW than that of the conventional structure, because holes are injected efficiently into the MQW along the p-type trench. It is also confirmed that the proposed structure also has a significant effect on strain relaxation and reduction in quantum confined stark effect by cathodo-luminescence (CL) measurement. In addition, two simple fabrication methods using e-beam lithography and selective wet etching for manufacturing the proposed structure are also proposed. From the measurement results of the manufactured GaN-based LEDs, it is confirmed that the proposed structure using e-beam lithography or selective wet etching shows improved light output power compared to the conventional structure because of more uniform hole distribution and strain relaxation effect. From this study, methods for analyzing the IQE of the GaN-based LEDs and its limiting factors are proposed and verified. It is also demonstrated that the p-type trench structure in the MQW will be the promising candidate for solving the efficiency droop problem of the GaN-based LEDs.Chapter1 Introduction 1.1 BACKGROUND 1.2 THESIS OUTLINE Chapter 2 Extraction of IQE and recombination coefficients by measuring transient characteristics 2.1 MODEL DESCRIPTION AND EXPERIMENTAL SETUP 2.2 EFFECTIVE VOLUME OF THE ACTIVE REGION 2.3 EXTRACTION OF RECOMBINATION COEFFICIENTS 2.4 CALCULATION OF INTERNAL QUANTUM EFFICIENCY 18 Chapter 3 Analysis of trap and its impact 3.1 EXPERIMENTAL PROCEDURE 3.2 EXTRACTION OF TRAP ACTIVATION ENERGY 3.3 EFFECTS OF TRAPS ON GAN-BASED LEDS Chapter 4 p-type trench structure for improving IQE 4.1 PROPOSED STRUCTURE 4.2 TCAD SIMULATION RESULTS 4.3 TRENCH PATTERNING USING E-BEAM LITHOGRAPHY 4.4 TRENCH PATTERNING USING SELECTIVE WET ETCHING 4.5 MEASUREMENT RESULTS Chapter 5 ConclusionsDocto

Circuits Techniques for Wireless Sensing Systems in High-Temperature Environments

RÉSUMÉ Dans ce projet, nous proposons de nouvelles techniques d’intégration basées sur la technologie de nitrure de gallium (GaN). Ces techniques permettent de mettre en œuvre un système de transmission de données sans fil entièrement intégré dédié aux capteurs de surveillance pour des applications d'environnement hostile. Le travail nécessite de trouver une technologie capable de résister à l'environnement sévère, principalement à haute température, et de permettre un niveau d'intégration élevé. Le système réalisé serait le premier dispositif de transmission de données basé sur la technologie GaN. En plus de supporter les conditions de haute température (HT) dépassant 600 oC, le système de transmission sans fil attendu devrait fonctionner à travers une barrière métallique séparant le module émetteur du récepteur. Une revue de la littérature sur les applications en environnements hostiles ainsi que sur l'électronique correspondante a été réalisée pour sélectionner la technologie AlGaN/GaN HEMT (transistor à haute mobilité d'électrons) comme une technologie appropriée. Le kit de conception GaN500, fourni par le Conseil national de recherches du Canada (CNRC), a été adopté pour concevoir et mettre en œuvre le système proposé. Cette technologie a été initialement introduite pour desservir les applications radiofréquences (RF) et micro-ondes. Par conséquent, elle n'avait pas été validée pour concevoir et fabriquer des circuits intégrés analogiques et numériques complexes et son utilisation à des températures extrêmes n’était pas validée. Nous avons donc caractérisé à haute température des dispositifs fabriqués en GaN500 et des éléments passifs intégrés correspondants ont été réalisés. Ces composants ont été testés sur la plage de température comprise entre 25 et 600 oC dans cette thèse. Les résultats de caractérisation ont été utilisés pour extraire les modèles HT des HEMT intégrés et des éléments passifs à utiliser dans les simulations. En outre, plusieurs composants intégrés basés sur la technologie GaN500, notamment des NOT, NOR, NAND, XOR, XNOR, registres, éléments de délais et oscillateurs ont été mis en œuvre et testés en HT. Des circuits analogiques à base de GaN500, comprenant un amplificateur de tension, un comparateur, un redresseur simple alternance, un redresseur double alternance, une pompe de charge et une référence de tension ont également été mis en œuvre et testés en HT. Le système de transmission de données mis en œuvre se compose d'un module de modulation situé dans la partie émettrice et d'un module de démodulation situé dans la partie réceptrice.----------ABSTRACT In this project, we propose new integrated-circuit design techniques based on the Gallium Nitride (GaN) technology to implement a fully-integrated data transmission system dedicated to wireless sensing in harsh environment applications. The goal in this thesis is to find a proper technology able to withstand harsh-environments (HEs), mainly characterized by high temperatures, and to allow a high-integration level. The reported design is the first data transmission system based on GaN technology. In addition to high temperature (HT) environment exceeding 600 oC, the expected wireless transmission systems may need to operate through metallic barriers separating the transmitting from the receiving modules. A wide literature review on the HE applications and corresponding electronics has been done to select the AlGaN/GaN HEMT (high-electron-mobility transistor) technology. The GaN500 design kit, provided by National Research Council of Canada (NRC), was adopted to design and implement the proposed system. This technology was initially provided to serve radio frequency (RF) and microwave circuits and applications. Consequently, it was not validated to implement complex integrated systems and to withstand extreme temperatures. Therefore, the high-temperature characterization of fabricated GaN500 devices and corresponding integrated passive elements was performed over the temperature range 25-600 oC in this thesis. The characterization results were used to extract HT models of the integrated HEMTs and passive elements to be used in simulations. Also, several GaN500-based digital circuits including NOT, NOR, NAND, XOR, XNOR, register, Delay and Ring oscillator were implemented and tested at HT. GaN500-based Analog circuits including front-end amplifier, comparator, half-bridge rectifier, full-bridge rectifier, charge pump and voltage reference were implemented and tested at HT as well. The implemented data transmission system consists of a modulation module located in the transmitting part and a demodulation block located in the receiving part. The proposed modulation system is based on the delta-sigma modulation technique and composed of a front-end amplifier, a comparator, a register, a charge pump and a ring oscillator. The output stage of the transmitter is intended to perform the load-shift-keying (LSK) modulation required to accomplish the data transmission through the dedicated inductive link. At the receiver level, three demodulation topologies were proposed to acquire the delivered LSK-modulated signals

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Monolayer doping of bulk and thin body group IV semiconductors

The turn of the new year from 2019-2020 has brought us into a new decade with an unforeseen worldwide halt to what was previously considered “normal” life, due to a virus (coronavirus-19) with dimensions measured by scanning electron microscopy (SEM) to be in the nanometre range. This has emphasized the importance for the general public of acknowledging particles and materials in this nanometre range which cannot be seen without electron microscopy. Some of the technology being used to fight these viruses, such as ventilators, operate using electronics which contain semiconductor materials. Since the mid 1900 s the size of these electronics has decreased while doubling their quantity of transistors in line with Moore’s law. This has allowed for increased performance with lower power consumption. Scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) has progressed from the original micrometre range to current sub-10 nm dimensions, while also moving from planar to 3-dimensional (3-D) architectures. However, increasing difficulty has been found with these new and reduced material dimensions. All fabrication processes are stressed, but doping has particularly found limitations in this region. High concentrations of dopant atoms are required at increasingly shallow depths, while maintaining the crystalline integrity of the planar or 3-D doped substrate. Traditional methods of introducing these dopant atoms, such as ion implantation, have found difficulty with damage production and conformality on state-of-the-art applications. Monolayer doping, which is a method of semiconductor doping through chemical functionalisation of the target substrate with the required dopant-containing molecules, has shown promise as an alternative method for this state-of-the-art doping.The aim of this thesis is to study the potential of monolayer doping for application to materials used in current and future transistor devices

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts