4,809 research outputs found

    JWalk: a tool for lazy, systematic testing of java classes by design introspection and user interaction

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    Popular software testing tools, such as JUnit, allow frequent retesting of modified code; yet the manually created test scripts are often seriously incomplete. A unit-testing tool called JWalk has therefore been developed to address the need for systematic unit testing within the context of agile methods. The tool operates directly on the compiled code for Java classes and uses a new lazy method for inducing the changing design of a class on the fly. This is achieved partly through introspection, using Java’s reflection capability, and partly through interaction with the user, constructing and saving test oracles on the fly. Predictive rules reduce the number of oracle values that must be confirmed by the tester. Without human intervention, JWalk performs bounded exhaustive exploration of the class’s method protocols and may be directed to explore the space of algebraic constructions, or the intended design state-space of the tested class. With some human interaction, JWalk performs up to the equivalent of fully automated state-based testing, from a specification that was acquired incrementally

    Power Droop Reduction In Logic BIST By Scan Chain Reordering

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    Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scan-based Logic BIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time

    Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability

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    Finding The Lazy Programmer's Bugs

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    Traditionally developers and testers created huge numbers of explicit tests, enumerating interesting cases, perhaps biased by what they believe to be the current boundary conditions of the function being tested. Or at least, they were supposed to. A major step forward was the development of property testing. Property testing requires the user to write a few functional properties that are used to generate tests, and requires an external library or tool to create test data for the tests. As such many thousands of tests can be created for a single property. For the purely functional programming language Haskell there are several such libraries; for example QuickCheck [CH00], SmallCheck and Lazy SmallCheck [RNL08]. Unfortunately, property testing still requires the user to write explicit tests. Fortunately, we note there are already many implicit tests present in programs. Developers may throw assertion errors, or the compiler may silently insert runtime exceptions for incomplete pattern matches. We attempt to automate the testing process using these implicit tests. Our contributions are in four main areas: (1) We have developed algorithms to automatically infer appropriate constructors and functions needed to generate test data without requiring additional programmer work or annotations. (2) To combine the constructors and functions into test expressions we take advantage of Haskell's lazy evaluation semantics by applying the techniques of needed narrowing and lazy instantiation to guide generation. (3) We keep the type of test data at its most general, in order to prevent committing too early to monomorphic types that cause needless wasted tests. (4) We have developed novel ways of creating Haskell case expressions to inspect elements inside returned data structures, in order to discover exceptions that may be hidden by laziness, and to make our test data generation algorithm more expressive. In order to validate our claims, we have implemented these techniques in Irulan, a fully automatic tool for generating systematic black-box unit tests for Haskell library code. We have designed Irulan to generate high coverage test suites and detect common programming errors in the process

    Sequential generation of structured arrays and its deductive verification

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    International audienceA structured array is an array satisfying given constraints, such as being sorted or having no duplicate values. Generation of all arrays with a given structure up to some given length has many applications, including bounded exhaustive testing. A sequential generator of structured arrays can be defined by two C functions: the first one computes an initial array, and the second one steps from one array to the next one according to some total order on the set of arrays. We formally specify with ACSL annotations that the generated arrays satisfy the prescribed structural constraints (soundness property) and that the generation is in increasing lexicographic order (progress property). We refine this specification into two programming and specification patterns: one for generation in lexicographic order and one for generation by filtering the output of another generator. We distribute a library of generators instantiating these patterns. After adding suitable loop invariants we automatically prove the soundness and progress properties with the Frama-C platform

    A Family of Controllable Cellular Automata for Pseudorandom Number Generation

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    In this paper, we present a family of novel Pseudorandom Number Generators (PRNGs) based on Controllable Cellular Automata (CCA) ─ CCA0, CCA1, CCA2 (NCA), CCA3 (BCA), CCA4 (asymmetric NCA), CCA5, CCA6 and CCA7 PRNGs. The ENT and DIEHARD test suites are used to evaluate the randomness of these CCA PRNGs. The results show that their randomness is better than that of conventional CA and PCA PRNGs while they do not lose the structure simplicity of 1-d CA. Moreover, their randomness can be comparable to that of 2-d CA PRNGs. Furthermore, we integrate six different types of CCA PRNGs to form CCA PRNG groups to see if the randomness quality of such groups could exceed that of any individual CCA PRNG. Genetic Algorithm (GA) is used to evolve the configuration of the CCA PRNG groups. Randomness test results on the evolved CCA PRNG groups show that the randomness of the evolved groups is further improved compared with any individual CCA PRNG

    Iterative Antirandom Testing

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    The Quasigroup Block Cipher and its Analysis

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    This thesis discusses the Quasigroup Block Cipher (QGBC) and its analysis. We first present the basic form of the QGBC and then follow with improvements in memory consumption and security. As a means of analyzing the system, we utilize tools such as the NIST Statistical Test Suite, auto and crosscorrelation, then linear and algebraic cryptanalysis. Finally, as we review the results of these analyses, we propose improvements and suggest an algorithm suitable for low-cost FPGA implementation

    A Hardware Security Solution against Scan-Based Attacks

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    Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the device-under-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature
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