SYNTHESIS OF COMPOSITE LOGIC GATE IN QCA EMBEDDING UNDERLYING REGULAR CLOCKING

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design’s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation

NOVEL SINGLE LAYER FAULT TOLERANCE RCA CONSTRUCTION FOR QCA TECHNOLOGY

Quantum-dot Cellular Automata (QCA) technology has become a promising and accessible candidate that can be used for digital circuits implementation at Nanoscale, but the circuit design in the QCA technology has been limited due to fabrication high-defect rate. So, this issue is an interesting research topic in the QCA circuits design. In this study, a novel 3-input Fault Tolerance (FT) Majority Gate (MG) is developed. Accordingly, an efficient 1-bit QCA full adder is developed using the developed 3-input MG. Then, a new 4-bit FT QCA Ripple Carry Adder (RCA) is developed based on the proposed 1-bit FT QCA FA. The developed circuits are implemented in the QCADesigner tool version 2.0.3. The results indicate that the developed QCA circuits provide advantages compared to other QCA circuits in terms of double and single cell missing defect, area and delay time

Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

Design of Power-Efficient Structures of the CAM Cell using a New Approach in QCA Nanoelectronics Technology

Quantum-dot Cellular Automata (QCA) is a new emerging nano-electronic technology. Owing to its many fa-vorable features such as low energy requirements, high speed, and small size, QCA is being actively suggested as a future CMOS replacement by researchers. Many digital circuits have been introduced in QCA technology, most of them aiming to reach the function with optimum construction in terms of area, cell count and power consumption. The memory circuit is the main building block in the digital system therefore the researchers paid attention to design the memory cells with minimum requirements. In this paper, a new methodology is intro-duced to design two forms of CAM cell. The proposed designs required two 2:1 multiplexers, one OR gate and one inverter. The first proposed design reduces the power consumption by 53.3%, 35% and 25.9% at (0.5 Ek, 1 Ek, and 1.5 Ek) while the second design by 53.2%, 31.9% and 20.5% (0.5 Ek, 1 Ek, and 1.5 Ek) respectively

A Novel Reconfiguration Scheme in Quantum-Dot Cellular Automata for Energy Efficient Nanocomputing

Quantum-Dot Cellular Automata (QCA) is currently being investigated as an alternative to CMOS technology. There has been extensive study on a wide range of circuits from simple logical circuits such as adders to complex circuits such as 4-bit processors. At the same time, little if any work has been done in considering the possibility of reconfiguration to reduce power in QCA devices. This work presents one of the first such efforts when considering reconfigurable QCA architectures which are expected to be both robust and power efficient. We present a new reconfiguration scheme which is highly robust and is expected to dissipate less power with respect to conventional designs. An adder design based on the reconfiguration scheme will be presented in this thesis, with a detailed power analysis and comparison with existing designs. In order to overcome the problems of routing which comes with reconfigurability, a new wire crossing mechanism is also presented as part of this thesis

Designing memory cells with a novel approaches based on a new multiplexer in QCA Technology

Transistor-based CMOS technology has many drawbacks such that it cannot continue to follow the scaling of Moore’s law in the near future. These drawbacks lead researchers to think about alternatives. Quantum-dot Cellular Automata (QCA) is a nanotechnology that has unique features in terms of size and power consumption. QCA has the ability to represent binary numbers by electrons configuration. The memory circuit is a very important part of the digital system. In QCA technology, there are many approaches presented to accomplish memory cells in both RAM and CAM types. CAM is a type of memory used in high-speed applications. In this thesis, novel approaches to design memory cells are proposed. The proposed approaches are based on a 2:1 multiplexer. Using the proposed approach of RAM cell, a singular form of RAM cell (SFRAMC) is accomplished. In QCA technology, researchers strive to design electronic circuits with an emphasis on minimizing important metrics such as cell count, area, delay, cost and power consumption. The SFRAMC demonstrated significant improvements, with a reduction cell count, occupied area and power consumption by 25%, 24% and 36%. In terms of implementation cost, the SFRAMC saves 43% of the cost when compared to the previous best design. On the other hand, by using the proposed approach of CAM cell, two different structures of the QCA-CAM cell have been introduced. The first proposed CAM cell (FPCAMC) gives improvements in terms of cell count, and delay by 15% and 17% respectively. The second proposed CAM cell (SPCAMC) gives improvements in terms of cell count, and delay by 6% and 17% respectively. In terms of total power consumption, both FPCAMC and SPCAMC have an improvement of about 53% over the best-reported design. The above features of the proposed memory cells (RAM and CAM) could pave the road for designing energy-efficient and cost-efficient memory circuits in the future

Optimized design and performance analysis of novel comparator and full adder in nanoscale

Abstract: In a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimitable transistorless computation approach that is based on semiconductor substantial and a substitute for customary CMOS and VLSI archetype at nanoscale point which comprises a better switching frequency, enhanced scale integration and small extent. In the design of digital logic, a comparator is the essential forming component which implements the resemblance of two numbers and a binary full adder is a major entity in digital logic systems. This paper deals with an expanded layout of reversible 1-bit comparator and proficient full adder without wire-crossing in QCA. The proposed layouts are significantly declined in terms of area and cell complexity, assessed to other layouts and clock cycle is retained at least. Quantum costs of the proposed circuits are estimated and compared, that shows the proposed QCA layouts have lesser quantum cost equated to regular designs and the energy depletion by the circuits endorses the view of QCA nano-circuit attending as a substitute level for the completion of reversible computing. Under thermal unpredictability, the constancy of the proposed designs is evaluated which show the operating efficacy of the designs. The simulation outcomes in QCADesigner tool approve that the presented designs performs properly and can be operated as an extreme performing design in QCA technology