190 research outputs found
An Adaptive ECC Scheme for Runtime Write Failure Suppression of STT-RAM Cache
Spin-transfer torque random access memory (STT-RAM) features many attractive charac- teristics, including near-zero standby power, nanosecond access time, small footprint, etc. These properties make STT-RAM perfectly suitable for the applications that are subject to limited power and area budgets, i.e., on-chip cache. Write reliability is one of the major challenges in design of STT-RAM caches. To ensure design quality, error correction code (ECC) scheme is usually adopted in STT-RAM caches. However, it incurs significant hard- ware overhead. In observance of the dynamic error correcting requirements, in this work, we propose an adaptive ECC scheme to suppress the runtime write failures of STT-RAM cache with minimized hardware cost, in which the cache is partitioned into regions protected by different ECCs. The error rate of a data is speculated on-the-fly and the data is allocated to a partition that provides the needed error correcting capability. Moreover, to accom- modate the time-varying error correcting requirements of runtime data, the thresholds that determine data’s destination cache partition will be adaptively adjusted. Our experimental results show that compared to conventional ECC schemes, our scheme can save up to 80.2% ECC bit overhead with slightly degraded write reliability of the STT-RAM cache. Moreover, the detailed analysis shows that through simultaneous optimization in cache access patterns and reducing STT cell programming workload, our method outperforms conventional ECC design in power and energy consumptions
Autonomous spacecraft maintenance study group
A plan to incorporate autonomous spacecraft maintenance (ASM) capabilities into Air Force spacecraft by 1989 is outlined. It includes the successful operation of the spacecraft without ground operator intervention for extended periods of time. Mechanisms, along with a fault tolerant data processing system (including a nonvolatile backup memory) and an autonomous navigation capability, are needed to replace the routine servicing that is presently performed by the ground system. The state of the art fault handling capabilities of various spacecraft and computers are described, and a set conceptual design requirements needed to achieve ASM is established. Implementations for near term technology development needed for an ASM proof of concept demonstration by 1985, and a research agenda addressing long range academic research for an advanced ASM system for 1990s are established
ELECTRICAL CHARACTERIZATION, PHYSICS, MODELING AND RELIABILITY OF INNOVATIVE NON-VOLATILE MEMORIES
Enclosed in this thesis work it can be found the results of a three years long research
activity performed during the XXIV-th cycle of the Ph.D. school in Engineering Science of
the Università degli Studi di Ferrara. The topic of this work is concerned about the
electrical characterization, physics, modeling and reliability of innovative non-volatile
memories, addressing most of the proposed alternative to the floating-gate based
memories which currently are facing a technology dead end. Throughout the chapters of
this thesis it will be provided a detailed characterization of the envisioned replacements for
the common NOR and NAND Flash technologies into the near future embedded and
MPSoCs (Multi Processing System on Chip) systems. In Chapter 1 it will be introduced the
non-volatile memory technology with direct reference on nowadays Flash mainstream,
providing indications and comments on why the system designers should be forced to
change the approach to new memory concepts. In Chapter 2 it will be presented one of the
most studied post-floating gate memory technology for MPSoCs: the Phase Change
Memory. The results of an extensive electrical characterization performed on these
devices led to important discoveries such as the kinematics of the erase operation and
potential reliability threats in memory operations. A modeling framework has been
developed to support the experimental results and to validate them on projected scaled
technology. In Chapter 3 an embedded memory for automotive environment will be shown:
the SimpleEE p-channel memory. The characterization of this memory proven the
technology robustness providing at the same time new insights on the erratic bits
phenomenon largely studied on NOR and NAND counterparts. Chapter 4 will show the
research studies performed on a memory device based on the Nano-MEMS concept. This
particular memory generation proves to be integrated in very harsh environment such as
military applications, geothermal and space avionics. A detailed study on the physical
principles underlying this memory will be presented. In Chapter 5 a successor of the
standard NAND Flash will be analyzed: the Charge Trapping NAND. This kind of memory
shares the same principles of the traditional floating gate technology except for the storage
medium which now has been substituted by a discrete nature storage (i.e. silicon nitride
traps). The conclusions and the results summary for each memory technology will be
provided in Chapter 6. Finally, on Appendix A it will be shown the results of a recently
started research activity on the high level reliability memory management exploiting the
results of the studies for Phase Change Memories
A polymorphic hardware platform
In the domain of spatial computing, it appears that platforms based on either reconfigurable datapath units or on hybrid microprocessor/logic cell organizations are in the ascendancy as they appear to offer the most efficient means of providing resources across the greatest range of hardware designs. This paper encompasses an initial exploration of an alternative organization. It looks at the effect of using a very fine-grained approach based on a largely undifferentiated logic cell that can be configured to operate as a state element, logic or interconnect - or combinations of all three. A vertical layout style hides the overheads imposed by reconfigurability to an extent where very fine-grained organizations become a viable option. It is demonstrated that the technique can be used to develop building blocks for both synchronous and asynchronous circuits, supporting the development of hybrid architectures such as globally asynchronous, locally synchronous
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