Generation and Analysis of Constrained Random Sampling Patterns

Random sampling is a technique for signal acquisition which is gaining popularity in practical signal processing systems. Nowadays, event-driven analog-to-digital converters make random sampling feasible in practical applications. A process of random sampling is defined by a sampling pattern, which indicates signal sampling points in time. Practical random sampling patterns are constrained by ADC characteristics and application requirements. In this paper authors introduce statistical methods which evaluate random sampling pattern generators with emphasis on practical applications. Furthermore, the authors propose a new random pattern generator which copes with strict practical limitations imposed on patterns, with possibly minimal loss in randomness of sampling. The proposed generator is compared with existing sampling pattern generators using the introduced statistical methods. It is shown that the proposed algorithm generates random sampling patterns dedicated for event-driven-ADCs better than existed sampling pattern generators. Finally, implementation issues of random sampling patterns are discussed.Comment: 29 pages, 12 figures, submitted to Circuits, Systems and Signal Processing journa

Optimal periodic sampling sequences for nearly-alias-free digital signal processing

Alias-free DSP (DASP) is a methodology of processing signals digitally inside bandwidths that are wider than the famous Nyquist limit of half of the sampling requency. DASP is facilitated by suitable combination of nonuniform sampling and appropriate processing algorithms. In this paper we propose a new method of constructing sampling schemes for the needs of DASP. Unlike traditional approaches that rely on randomly selected sampling instants we use deterministic schemes. A method of optimizing such sequences aimed at minimization of aliasing is proposed. The approach is tested numerically in an experiment where an undersampled signal is processed using DASP; first to estimate the signal's spectrum support function and then the spectrum itself. We demonstrate advantages of the proposed approach over those that use random sampling

Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy- Efficient Computing

With the explosion of the number of compute nodes, the bottleneck of future computing systems lies in the network architecture connecting the nodes. Addressing the bottleneck requires replacing current backplane-based network topologies. We propose to revolutionize computing electronics by realizing embedded optical waveguides for onboard networking and wireless chip-to-chip links at 200-GHz carrier frequency connecting neighboring boards in a rack. The control of novel rate-adaptive optical and mm-wave transceivers needs tight interlinking with the system software for runtime resource management

DASP Implementation of Continuous-Time, Finite-Impulse-Response Systems

Digital Alias-free Signal Processing (DASP) uses random sampling to mitigate aliasing. This paper investigates the use of DASP for realization of continuous-time, linear, time-invariant systems with finite-duration impulse response. We propose a random sampling scheme and suitable processing algorithm to produce an estimator of the target output. The estimator is unbiased, and its variance is guaranteed to converge to zero at least at O(T) rate, where T is the average distance between consecutive sampling instants. If the input signal and system impulse response are piecewise continuous and satisfy some benign conditions, the convergence rate is at least O(T^2). But if they are continuous everywhere, the rate increases to O(T^3)

Applications of nonuniform sampling in wideband multichannel communication systems

This research is an investigation into utilising randomised sampling in communication systems to ease the sampling rate requirements of digitally processing narrowband signals residing within a wide range of overseen frequencies. By harnessing the aliasing suppression capabilities of such sampling schemes, it is shown that certain processing tasks, namely spectrum sensing, can be performed at significantly low sampling rates compared to those demanded by uniform-sampling-based digital signal processing. The latter imposes sampling frequencies of at least twice the monitored bandwidth regardless of the spectral activity within. Aliasing can otherwise result in irresolvable processing problems, as the spectral support of the present signal is a priori unknown. Lower sampling rates exploit the processing module(s) resources (such as power) more efficiently and avoid the possible need for premium specialised high-cost DSP, especially if the handled bandwidth is considerably wide. A number of randomised sampling schemes are examined and appropriate spectral analysis tools are used to furnish their salient features. The adopted periodogram-type estimators are tailored to each of the schemes and their statistical characteristics are assessed for stationary, and cyclostationary signals. Their ability to alleviate the bandwidth limitation of uniform sampling is demonstrated and the smeared-aliasing defect that accompanies randomised sampling is also quantified. In employing the aforementioned analysis tools a novel wideband spectrum sensing approach is introduced. It permits the simultaneous sensing of a number of nonoverlapping spectral subbands constituting a wide range of monitored frequencies. The operational sampling rates of the sensing procedure are not limited or dictated by the overseen bandwidth antithetical to uniform-sampling-based techniques. Prescriptive guidelines are developed to ensure that the proposed technique satisfies certain detection probabilities predefined by the user. These recommendations address the trade-off between the required sampling rate and the length of the signal observation window (sensing time) in a given scenario. Various aspects of the introduced multiband spectrum sensing approach are investigated and its applicability highlighted

Behavioral modeling and FPGA implementation of digital predistortion for RF and microwave power amplifiers

With the high interest in digital modulation techniques which are very sensitive to the PA nonlinearity, modern wireless communication systems require the usage of linearization techniques to improve the linear behavior of the RF power amplifier. The powerful and cheap digital processing technology makes the digital predistortion (DPD) a competitive candidate for the linearization of the PA. This thesis introduces the basic principle of DPD, its implementation on FPGA and the adaptive DPD system. The linearization of 4 PAs with DPD technique has been introduced: for the hybrid class AB PA operating at 2.6 GHz with a WiMAX testing signal, 33.7 dBm average power, 29.6 % drain efficiency, 13 dB ACPR and 9 dB NMSE improvement have been obtained; for the hybrid Doherty PA operating at 3.4 GHz with an I/Q testing signal, 35.0 dBm average power, 36.8 % drain efficiency, 12 dB ACPR and 13 dB NMSE improvement have been obtained; for the MMIC class AB PA operating at 7 GHz with an I/Q testing signal, 29.4 dBm average power, 25.7 % drain efficiency, 12 dB ACPR and 12 dB NMSE improvement have been obtained; for the two-stage PA operating at 24 GHz with an I/Q testing signal, 23.5 dBm average power, more than 14.0 % drain efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The DPD algorithm has been implemented on FPGA with two methods based on LUT and a direct structure with only adders and multipliers. The block RAM on the FPGA board is chosen as the table in the LUT methods. The linearization performance for these three methods is similar. The test PA is the hybrid Doherty PA mentioned above and the test signal is the I/Q signal with 7.4 dB PAPR. 35.1 dBm average power, 36.8 % efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The cost of logic resources for the direct structure method is the largest with 1,172 flip-flops, while the number of flip-flops for the two LUT methods are 263 and 583, respectively. A new adaptive algorithm has been proposed in this thesis for the adaptive DPD system. This new algorithm improves the performance in extracting the model parameters in complex number domain. With the experimental data from a combined class AB PA, the final accuracy of the model extracted by the new algorithm has been improved from -20 dB to about -40 dB and the converge speed is faster

Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing

Digital Signal Processing Techniques Applied to Radio over Fiber Systems

The dissertation aims to analyze different Radio over Fiber systems for the front-haul applications. Particularly, analog radio over fiber (A-RoF) are simplest and suffer from nonlinearities, therefore, mitigating such nonlinearities through digital predistortion are studied. In particular for the long haul A-RoF links, direct digital predistortion technique (DPDT) is proposed which can be applied to reduce the impairments of A-RoF systems due to the combined effects of frequency chirp of the laser source and chromatic dispersion of the optical channel. Then, indirect learning architecture (ILA) based structures namely memory polynomial (MP), generalized memory polynomial (GMP) and decomposed vector rotation (DVR) models are employed to perform adaptive digital predistortion with low complexities. Distributed feedback (DFB) laser and vertical capacity surface emitting lasers (VCSELs) in combination with single mode/multi-mode fibers have been linearized with different quadrature amplitude modulation (QAM) formats for single and multichannel cases. Finally, a feedback adaptive DPD compensation is proposed. Then, there is still a possibility to exploit the other realizations of RoF namely digital radio over fiber (D-RoF) system where signal is digitized and transmits the digitized bit streams via digital optical communication links. The proposed solution is robust and immune to nonlinearities up-to 70 km of link length. Lastly, in light of disadvantages coming from A-RoF and D-RoF, it is still possible to take only the advantages from both methods and implement a more recent form knows as Sigma Delta Radio over Fiber (S-DRoF) system. Second Order Sigma Delta Modulator and Multi-stAge-noise-SHaping (MASH) based Sigma Delta Modulator are proposed. The workbench has been evaluated for 20 MHz LTE signal with 256 QAM modulation. Finally, The 6x2 GSa/s sigma delta modulators are realized on FPGA to show a real time demonstration of S-DRoF system. The demonstration shows that S-DRoF is a competitive competitor for 5G sub-6GHz band applications