31 research outputs found
2013-2014 Bulletin
After 2003 the University of Dayton Bulletin went exclusively online. This copy was downloaded from the University of Dayton\u27s website.https://ecommons.udayton.edu/bulletin/1012/thumbnail.jp
2012-2013 Bulletin
After 2003 the University of Dayton Bulletin went exclusively online. This copy was downloaded from the University of Dayton\u27s website.https://ecommons.udayton.edu/bulletin/1011/thumbnail.jp
Efficient emulation of MIMD behavior on SIMD machines
SIMD computers have proved to be a useful and cost effective approach
to massively parallel computation. On the other hand, there are
algorithms which are very inefficient when directly translated into a
data-parallel program.This paper presents a number of simple
transformations which are able to reduce this SIMD overhead to
a moderate constant factor. It also introduces techniques for
reducing the remaining overhead using Markov chain models of control
flow. The optimization problems involved are NP-hard in general but
there are many useful heuristics, and closed form optimizations for a
probabilistic variant
A configurable vector processor for accelerating speech coding algorithms
The growing demand for voice-over-packer (VoIP) services and multimedia-rich
applications has made increasingly important the efficient, real-time implementation of
low-bit rates speech coders on embedded VLSI platforms. Such speech coders are
designed to substantially reduce the bandwidth requirements thus enabling dense multichannel
gateways in small form factor. This however comes at a high computational cost
which mandates the use of very high performance embedded processors.
This thesis investigates the potential acceleration of two major ITU-T speech coding
algorithms, namely G.729A and G.723.1, through their efficient implementation on a
configurable extensible vector embedded CPU architecture. New scalar and vector ISAs
were introduced which resulted in up to 80% reduction in the dynamic instruction count
of both workloads. These instructions were subsequently encapsulated into a parametric,
hybrid SISD (scalar processor)–SIMD (vector) processor. This work presents the research
and implementation of the vector datapath of this vector coprocessor which is tightly-coupled
to a Sparc-V8 compliant CPU, the optimization and simulation methodologies
employed and the use of Electronic System Level (ESL) techniques to rapidly design
SIMD datapaths
2002-2003 Bulletin
Volume 112, Number 1
Scanned from the copy held in the Registrar\u27s Office.https://ecommons.udayton.edu/bulletin_grad/1031/thumbnail.jp
2002-2003 Bulletin
Volume 113, Number 4.
Scanned from the copy held in the Registrar\u27s Office.https://ecommons.udayton.edu/bulletin/1047/thumbnail.jp
2001-2002 Bulletin
Volume 112, Number 4
Scanned from the copy held in University Archives and Special Collections.https://ecommons.udayton.edu/bulletin/1069/thumbnail.jp
2000-2001 Bulletin
Volume 110, Number 1
Scanned from the copy held in the Registrar\u27s Office.https://ecommons.udayton.edu/bulletin_grad/1030/thumbnail.jp
2000-2001 Bulletin
Volume 111, Number 4.
Scanned from the copy held in the Registrar\u27s Office.https://ecommons.udayton.edu/bulletin/1046/thumbnail.jp
1999-2000 Bulletin
Volume 110, Number 4
Scanned from the copy held in University Archives and Special Collections.https://ecommons.udayton.edu/bulletin/1068/thumbnail.jp