Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Low Power Adaptive Circuits: An Adaptive Log Domain Filter and A Low Power Temperature Insensitive Oscillator Applied in Smart Dust Radio

This dissertation focuses on exploring two low power adaptive circuits. One is an adaptive filter at audio frequency for system identification. The other is a temperature insensitive oscillator for low power radio frequency communication. The adaptive filter is presented with integrated learning rules for model reference estimation. The system is a first order low pass filter with two parameters: gain and cut-off frequency. It is implemented using multiple input floating gate transistors to realize online learning of system parameters. Adaptive dynamical system theory is used to derive robust control laws in a system identification task. Simulation results show that convergence is slower using simplified control laws but still occurs within milliseconds. Experimental results confirm that the estimated gain and cut-off frequency track the corresponding parameters of the reference filter. During operation, deterministic errors are introduced by mismatch within the analog circuit implementation. An analysis is presented which attributes the errors to current mirror mismatch. The harmonic distortion of the filter operating in different inversion is analyzed using EKV model numerically. The temperature insensitive oscillator is designed for a low power wireless network. The system is based on a current starved ring oscillator implemented using CMOS transistors instead of LC tank for less chip area and power consumption. The frequency variance with temperature is compensated by the temperature adaptive circuits. Experimental results show that the frequency stability from 5°C to 65°C has been improved 10 times with automatic compensation and at least 1 order less power is consumed than published competitors. This oscillator is applied in a 2.2GHz OOK transmitter and a 2.2GHz phase locked loop based FM receiver. With the increasing needs of compact antenna, possible high data rate and wide unused frequency range of short distance communication, a higher frequency phase locked loop used for BFSK receiver is explored using an LC oscillator for its capability at 20GHz. The success of frequency demodulation is demonstrated in the simulation results that the PLL can lock in 0.5μs with 35MHz lock-in range and 2MHz detection resolution. The model of a phase locked loop used for BFSK receiver is analyzed using Matlab

Switched-capacitor step-down rectifier for low-voltage power conversion

This paper presents a switched-capacitor rectifier that provides step down voltage conversion from an ac input voltage to a dc output. Coupled with current-drive source, low-loss and high step-down rectification is realized. Implementation in CMOS with appropriate controls results in a design suitable for low-voltage very-high-frequency conversion. Applications include switched-capacitor rectification to convert high-frequency ac to a dc output and, combined with inversion and transformation, to dc-dc converters for low-voltage outputs. A two-step CMOS integrated full-bridge switched-capacitor rectifier is implemented in TSMC 0.25 μm CMOS technology for demonstration purposes. For an operation frequency of 50 MHz and an output voltage of 2.5 V, the peak efficiency of the rectifier is 81% at a power level of 4 W.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation

A hardware and software platform for characterization and prototyping of a low-power energy-harvesting SoC

Energy consumption is an important performance indicator for wireless devices. Developing ICs that address this issue for IoT applications is a complex task, which relies not only on design, but also on testing and characterization as a large part of the process. This thesis develops a framework for testing, characterizing and prototyping of an ultra-low power IC developed at Aalto. The framework consists of both hardware and software components. The hardware involves a large four-layer PCB, various components that support the IC’s functions and a smaller PCB which interfaces with a one-bit display, both implemented with Altium Designer, together with a UWBfilter and an impedance matching network. The software part consists of a flexible IC programming and configuration interface written in Python, two LabVIEW VIs for wireless data transmission and reception and a set of measurement automation libraries written in Python. The framework is successfully tested with the one-bit display driver and is used by the researchers for evaluating their IC blocks

Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing

Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Analysis and Design of 3-Phase Unfolding Based AC-DC Battery Chargers

This thesis presents the analysis and design of high-efficiency battery chargers for heavy duty EV applications. The rise in popularity of the electric vehicles (EVs) due to their increased efficiency over conventional internal combustion engines, has driven the need for more battery charging infrastructure. Furthermore, heavy duty vehicles are also being converted to electric to fill needs such as public transportation via bus fleets as well as cargo delivery via semi-trucks. Such heavy duty vehicles require more energy than personal transportation vehicles and thus require larger battery packs. To charge heavy duty battery packs in the same amount of time as the typical EV, higher power chargers are required. Energy is distributed through the grid network, and a battery charger is converts the grid power into a regulated output for battery charging. The novel battery charging designs investigated in this thesis are classified differently than traditional designs because they have fewer switching stages to convert the power. The unique approach taken allows these designs to have higher efficiency overall than a traditional battery charger design. The new converter designs are refereed to as the three-level (3L) asymmetrical full bridge (3LAFB)and 3L asymmetrical dual active bridge (3LADAB). The operation of each converter is briefly discussed to help develop context for the hardware and controller designs. The controller design for the 3LAFB topology is developed to explain the control objectives of the 3-port dc-dc converter. Hardware results prototype designs are presented to validate proposed chargers and controller designs. A high power extreme fast charger (XFC) structure is proposed using multiple lower power modules. The high-efficiency design of a single module is presented and hardware results are given