First order devices, hybrid memristors, and the frontiers of nonlinear circuit theory

Several devices exhibiting memory effects have shown up in nonlinear circuit theory in recent years. Among others, these circuit elements include Chua's memristors, as well as memcapacitors and meminductors. These and other related devices seem to be beyond the, say, classical scope of circuit theory, which is formulated in terms of resistors, capacitors, inductors, and voltage and current sources. We explore in this paper the potential extent of nonlinear circuit theory by classifying such mem-devices in terms of the variables involved in their constitutive relations and the notions of the differential- and the state-order of a device. Within this framework, the frontier of first order circuit theory is defined by so-called hybrid memristors, which are proposed here to accommodate a characteristic relating all four fundamental circuit variables. Devices with differential order two and mem-systems are discussed in less detail. We allow for fully nonlinear characteristics in all circuit elements, arriving at a rather exhaustive taxonomy of C^1-devices. Additionally, we extend the notion of a topologically degenerate configuration to circuits with memcapacitors, meminductors and all types of memristors, and characterize the differential-algebraic index of nodal models of such circuits.Comment: Published in 2013. Journal reference included as a footnote in the first pag

Observation of chaotic beats in a driven memristive Chua's circuit

In this paper, a time varying resistive circuit realising the action of an active three segment piecewise linear flux controlled memristor is proposed. Using this as the nonlinearity, a driven Chua's circuit is implemented. The phenomenon of chaotic beats in this circuit is observed for a suitable choice of parameters. The memristor acts as a chaotically time varying resistor (CTVR), switching between a less conductive OFF state and a more conductive ON state. This chaotic switching is governed by the dynamics of the driven Chua's circuit of which the memristor is an integral part. The occurrence of beats is essentially due to the interaction of the memristor aided self oscillations of the circuit and the external driving sinusoidal forcing. Upon slight tuning/detuning of the frequencies of the memristor switching and that of the external force, constructive and destructive interferences occur leading to revivals and collapses in amplitudes of the circuit variables, which we refer as chaotic beats. Numerical simulations and Multisim modelling as well as statistical analyses have been carried out to observe as well as to understand and verify the mechanism leading to chaotic beats.Comment: 30 pages, 16 figures; Submitted to IJB

A Frequency Domain Analysis of the Excitability and Bifurcations of the FitzHugh–Nagumo Neuron Model

The dynamics of neurons consist of oscillating patterns of a membrane potential that underpin the operation of biological intelligence. The FitzHugh−Nagumo (FHN) model for neuron excitability generates rich dynamical regimes with a simpler mathematical structure than the Hodgkin−Huxley model. Because neurons can be understood in terms of electrical and electrochemical methods, here we apply the analysis of the impedance response to obtain the characteristic spectra and their evolution as a function of applied voltage. We convert the two nonlinear differential equations of FHN into an equivalent circuit model, classify the different impedance spectra, and calculate the corresponding trajectories in the phase plane of the variables. In analogy to the field of electrochemical oscillators, impedance spectroscopy detects the Hopf bifurcations and the spiking regimes. We show that a neuron element needs three essential internal components: capacitor, inductor, and negative differential resistance. The method supports the fabrication of memristor-based artificial neural networks

Hybrid analysis of nonlinear circuits: DAE models with indices zero and one

We extend in this paper some previous results concerning the differential-algebraic index of hybrid models of electrical and electronic circuits. Specifically, we present a comprehensive index characterization which holds without passivity requirements, in contrast to previous approaches, and which applies to nonlinear circuits composed of uncoupled, one-port devices. The index conditions, which are stated in terms of the forest structure of certain digraph minors, do not depend on the specific tree chosen in the formulation of the hybrid equations. Additionally, we show how to include memristors in hybrid circuit models; in this direction, we extend the index analysis to circuits including active memristors, which have been recently used in the design of nonlinear oscillators and chaotic circuits. We also discuss the extension of these results to circuits with controlled sources, making our framework of interest in the analysis of circuits with transistors, amplifiers, and other multiterminal devices

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Parity-time symmetric systems with memory

Classical open systems with balanced gain and loss, i.e. parity-time ($\mathcal{PT}$) symmetric systems, have attracted tremendous attention over the past decade. Their exotic properties arise from exceptional point (EP) degeneracies of non-Hermitian Hamiltonians that govern their dynamics. In recent years, increasingly sophisticated models of $\mathcal{PT}$-symmetric systems with time-periodic (Floquet) driving, time-periodic gain and loss, and time-delayed coupling have been investigated, and such systems have been realized across numerous platforms comprising optics, acoustics, mechanical oscillators, optomechanics, and electrical circuits. Here, we introduce a $\mathcal{PT}$-symmetric (balanced gain and loss) system with memory, and investigate its dynamics analytically and numerically. Our model consists of two coupled $LC$ oscillators with positive and negative resistance, respectively. We introduce memory by replacing either the resistor with a memristor, or the coupling inductor with a meminductor, and investigate the circuit energy dynamics as characterized by $\mathcal{PT}$-symmetric or $\mathcal{PT}$-symmetry broken phases. Due to the resulting nonlinearity, we find that energy dynamics depend on the sign and strength of initial voltages and currents, as well as the distribution of initial circuit energy across its different components. Surprisingly, at strong inputs, the system exhibits self-organized Floquet dynamics, including $\mathcal{PT}$-symmetry broken phase at vanishingly small dissipation strength. Our results indicate that $\mathcal{PT}$-symmetric systems with memory show a rich landscape