The DSP-Carrier Board Used by the LEIR Low-Level RF System: User's Manual

A new digital technology to implement beam control systems was tested in the PS Booster in 2004 and 2005 and commissioned in LEIR in 2006. The technology is based upon RF custom hardware that heavily exploits Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs) processing power. This architecture is extremely flexible in that it relies on a DSP-carrier board hosting one DSP and carrying different daughtercards. The LEIR beam control system deploys three DSP-carrier boards, which inter-communicate and exchange data continuously for the implementation of the various beam control loops. This user's manual for the DSP-carrier board, release 1.0 (EDA-00990-V1), was written in 2004 and has been used by CERN and BNL developers since then. It describes the DSP-carrier board hardware, user settings and FPGA software; hints on the DSP code used with the board are also given. An additional VME board, called Rear Transition Module, is described because it acts as a DSP-carrier board extension

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Bare Metal Porting of Tasking Framework on a Xilinx Board

The Tasking Framework is DLR’s solution for distributed and parallel computation. In many aspects this can be considered similar to an Operating system which does not have any computation functions of its own. It provides access to the resources like CPU time for tasks which require processing. These tasks can be requests from any sensor to process its data which could be crucial in attitude control of a space craft. This particular framework is currently employed by DLR in many of their existing projects. Each of these projects has different hardware requirements and hence the platform on which the framework is implemented differs from project to project. In order to have some uniformity and to reduce the efforts for more such implementations, the entire framework is divided into an API and a hardware dependent layer. As part of this project the API is relatively unchanged. All the modifications and changes are to be made only in the hardware dependent layer. The objective of this internship is to achieve a bare metal implementation of this framework. In all the existing implementations there has always been an underlying operating system. In this case the operating system is inexistent. The idea is stemmed from the observations made regarding excessive usage of resources, undesired over heads etc. when an operating system is running. The hardware selected for this implementation is provided by Xilinx. The evaluation board is based on Xilinx’s popular Zynq architecture. It comes with two ARM cortex A9 based processors which forms the core of the processing system on the board. It also accommodates an FPGA block which can be configured for specific purposes and used as a third processor for sharing the workload. In this internship however the FPGA was not used. The FPGA is however mapped with a bitstream file generated using the Vivado software package to be able to access the other peripherals. The implementation was successfully carried out and SMP architecture is implemented for sharing the workload between the two available processors

Minimalistic SDHC-SPI hardware reader module for boot loader applications

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software boot loader and the related memory resources. The hardware overhead introduced is manageable, even in low-range FPGA chips, and negligible in mid- and high-range devices. The implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller

NASA SpaceCube Intelligent Multi-Purpose System for Enabling Remote Sensing, Communication, and Navigation in Mission Architectures

New, innovative CubeSat mission concepts demand modern capabilities such as artificial intelligence and autonomy, constellation coordination, fault mitigation, and robotic servicing – all of which require vastly more processing resources than legacy systems are capable of providing. Enabling these domains within a scalable, configurable processing architecture is advantageous because it also allows for the flexibility to address varying mission roles, such as a command and data-handling system, a high-performance application processor extension, a guidance and navigation solution, or an instrument/sensor interface. This paper describes the NASA SpaceCube Intelligent Multi-Purpose System (IMPS), which allows mission developers to mix-and-match 1U (10 cm × 10 cm) CubeSat payloads configured for mission-specific needs. The central enabling component of the system architecture to address these concerns is the SpaceCube v3.0 Mini Processor. This single-board computer features the 20nm Xilinx Kintex UltraScale FPGA combined with a radiation-hardened FPGA monitor, and extensive IO to integrate and interconnect varying cards within the system. To unify the re-usable designs within this architecture, the CubeSat Card Standard was developed to guide design of 1U cards. This standard defines pinout configurations, mechanical, and electrical specifications for 1U CubeSat cards, allowing the backplane and mechanical enclosure to be easily extended. NASA has developed several cards adhering to the standard (System-on-Chip, power card, etc.), which allows the flexibility to configure a payload from a common catalog of cards

CubeSat Data Transmission and Storage Throughput Optimization Through the Use of a Zynq SoC Based CubeSat Science Instrument Interface Electronics Board

The CubeSat standard sprang from the desire to create a satellite standard that would open the doors for universities and other lower budget research institutions by making it more feasible to get their work into space. Since then, many other institutions and industries have been adopting variations on the standard for their own use. As more people are seeking out to use the CubeSat standard as their main bus, the standards and practices of the community have grown and expanded and with this growth, new challenges have been created. One such challenge is the bandwidth limitation in the RF-downlink. When carrying payloads requiring what might seem to be a relatively small (science data) bandwidth requirement (on the order of thousands of bps), the RF-link to ground is overloaded. Many approaches in the past have been put forth to help alleviate this issue, unfortunately, none have been fully adopted. This paper presents a solution that takes advantage of new technology yet to be fully exploited in space applications. The key to the solution lies in removing the bandwidth requirements by enabling onboard post-data processing and compression. In order to achieve the high computational needs, while minimizing power consumption, a Xilinx Zynq-7000 SoC is used, creating a highly-programmable, open integration device. This report outlines the design, fabrication and testing of this solution. The completion of the Zynq Processing System CubeSat Science Instrument Interface Electronics Board (or ZPS-Board), ultimately demonstrates the feasibility of this solution. Additionally, this research is funded by NASA’s JPL, with secondary motives for the creating of a space application Zynq-7000 SoC based product. Upon successful completion of the ZPS-Board, the product creates a platform for JPL to perform environmental testing in order to study the effects and performance characteristics of the Zynq in space applications