Disseny microelectrnic de circuits discriminadors de polsos pel detector LHCb

The aim of this thesis is to present a solution for implementing the front end system of the Scintillator Pad Detector (SPD) of the calorimeter system of the LHCb experiment that will start in 2008 at the Large Hadron Collider (LHC) at CERN. The requirements of this specific system are discussed and an integrated solution is presented, both at system and circuit level. We also report some methodological achievements. In first place, a method to study the PSRR (and any transfer function) in fully differential circuits taking into account the effect of parameter mismatch is proposed. Concerning noise analysis, a method to study time variant circuits in the frequency domain is presented and justified. This would open the possibility to study the effect of 1/f noise in time variants circuits. In addition, it will be shown that the architecture developed for this system is a general solution for front ends in high luminosity experiments that must be operated with no dead time and must be robust against ballistic deficit

Noise-Sensitive Loops Identification for Linear Time-Varying Analog Circuits

The continuing scaling of VLSI technology and the increase of design complexity have rendered the robustness of analog circuits a significant design concern. Analog circuits with strong parasitic effects can be modeled using a multi-loop structure, which is more sophisticated than the traditional single feedback loop structure and results in a more complex small signal stability analysis from the noise perspective. A Loop Finder algorithm has been proposed to allow designers to detect and identify noise-sensitive return loops, which are also called "unstable" loops in previous works, without the need to add breakpoints in the circuit. Besides, efficient pole discovery and impedance computation methods have been explored so that the Loop Finder algorithm can deal with very large scale analog circuits in a reasonable amount of time. However, this algorithm only works for circuits that can be described using a linear time-invariant (LTI) system model. Many practical circuits, such as switch capacitor filters, mixers and so on, have time-varying behaviors. To describe such circuits, a linear time-varying (LTV) system model needs to be employed. In this research, we first examine the stability property of LTV systems in time domain, mostly based upon the Floquet Theory. We then take an in-depth look at the transfer function of an LTV system in the frequency domain and build the link between it and the Floquet theory. Finally, we propose an efficient algorithm for identifying noise-sensitive loops in linear time-varying circuits. This methodology provides a unifying solution for loop-based noise analysis for both LTI and LTV circuits

Influence of jitter on limit cycles in bang-bang clock and data recovery circuits

In bang-bang (BB) clock and data recovery circuits (CDR) limit cycles can occur, but these limit cycles are undesired for a good operation of the BB-CDR. Surprisingly, however, a little bit of noise in the system is beneficial, because it will quench the limit cycles. Until now, authors have always assumed that there is enough noise in a BB-CDR such that no limit cycle occurs. In this work, a pseudo-linear analysis based on describing functions is used to investigate this. In particular, the relationship between the input noise and the amplitude of eventual limit cycles is investigated. An important result of the theory is that it allows to quantify the influence of the different loop parameters on the minimal amount of input jitter needed to destroy the limit cycle. Additionally, for the case that there is not enough noise, the worst case amplitude of the limit cycle (which is unavoidable in this case) is quantified as well. The presented analysis exhibits excellent matching with time domain simulations and leads to very simple analytical expressions

Compact modeling technology for the simulation of integrated circuits based on graphene field-effect transistors

transformatiu CRUE-CSICUTP en procés de revisióAltres ajuts: GraphCAT project reference 001-P-001702The progress made toward the definition of a modular compact modeling technology for graphene field-effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET-based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non-idealities, such as extrinsic-, short-channel-, trapping/detrapping-, self-heating-, and non-quasi static-effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Variable domain transformation for linear PAC analysis of mixed-signal systems

This paper describes a method to perform linear AC analysis on mixed-signal systems which appear strongly nonlinear in the voltage domain but are linear in other variable domains. Common circuits like phase/delay-locked loops and duty-cycle correctors fall into this category, since they are designed to be linear with respect to phases, delays, and duty-cycles of the input and output clocks, respectively. The method uses variable domain translators to change the variables to which the AC perturbation is applied and from which the AC response is measured. By utilizing the efficient periodic AC (PAC) analysis available in commercial RF simulators, the circuit’s linear transfer function in the desired variable domain can be characterized without relying on extensive transient simulations. Furthermore, the variable domain translators enable the circuits to be macromodeled as weakly-nonlinear systems in the chosen domain and then converted to voltage-domain models, instead of being modeled as strongly-nonlinear systems directly

Large-signal device simulation in time- and frequency-domain: a comparison

The aim of this paper is to compare the most common time- and frequency-domain numerical techniques for the determination of the steady-state solution in the physics-based simulation of a semiconductor device driven by a time-periodic generator. The shooting and harmonic balance (HB) techniques are applied to the solution of the discretized drift-diffusion device model coupled to the external circuit embedding the semiconductor device, thus providing a fully nonlinear mixed mode simulation. The comparison highlights the strong and weak points of the two approaches, basically showing that the time-domain solution is more robust with respect to the initial condition, while the HB solution provides a more rapid convergence once the initial datum is close enough to the solution itsel