Characterization of a Single Photon Sensing and Photon Number Resolving CMOS Detector for Astrophysics

Next-generation NASA missions, such as the LUVIOR and HabEx concepts, require single photon counting large-format detectors. Charge Coupled Devices (CCDs) have typically been used for optical applications in similar flagship missions of the past. CCDs have excellent properties in most metrics but have their own challenges for single photon counting applications. First, typical CCDs have a read noise of a few electrons, although recent modifications (EMCCDs) use an on-chip gain to amplify the signal above the read noise. Secondly, the signal is carried by charge that is transferred across the detector array. While CCDs for NASA missions are carefully fabricated to minimize defects, continuous bombardment from high energy radiation in space will damage the detector over the lifetime of the mission. This will degrade the charge transfer efficiency and in turn, reduce the single photon counting ability of the CCD. CMOS devices offer a different architecture that mitigates some of these problems. In CMOS image sensors, each pixel has its own charge to voltage converter and in-pixel amplifier mitigating issues found with charge transfer efficiency. Additional circuits that are critical to operation of the sensor can be incorporated on chip allowing for a parallel readout architecture that increases frame rate and can decrease read noise. This thesis is a collection of work for the characterization of a room temperature characterization, low-noise, single photon counting and photon number resolving CMOS detector. The work performed in this thesis will provide the framework for a technology development project funded by NASA Cosmic Origins (COR) program office. At the end of the two-year project, a megapixel CMOS focal plane array will be demonstrated to satisfy the stated needs of the LUVOIR and HabEx future astrophysics space mission concepts with a launch date near the 2040s

High Speed Camera Chip

abstract: The market for high speed camera chips, or image sensors, has experienced rapid growth over the past decades owing to its broad application space in security, biomedical equipment, and mobile devices. CMOS (complementary metal-oxide-semiconductor) technology has significantly improved the performance of the high speed camera chip by enabling the monolithic integration of pixel circuits and on-chip analog-to-digital conversion. However, for low light intensity applications, many CMOS image sensors have a sub-optimum dynamic range, particularly in high speed operation. Thus the requirements for a sensor to have a high frame rate and high fill factor is attracting more attention. Another drawback for the high speed camera chip is its high power demands due to its high operating frequency. Therefore, a CMOS image sensor with high frame rate, high fill factor, high voltage range and low power is difficult to realize. This thesis presents the design of pixel circuit, the pixel array and column readout chain for a high speed camera chip. An integrated PN (positive-negative) junction photodiode and an accompanying ten transistor pixel circuit are implemented using a 0.18 µm CMOS technology. Multiple methods are applied to minimize the subthreshold currents, which is critical for low light detection. A layout sharing technique is used to increase the fill factor to 64.63%. Four programmable gain amplifiers (PGAs) and 10-bit pipeline analog-to-digital converters (ADCs) are added to complete on-chip analog to digital conversion. The simulation results of extracted circuit indicate ENOB (effective number of bits) is greater than 8 bits with FoM (figures of merit) =0.789. The minimum detectable voltage level is determined to be 470μV based on noise analysis. The total power consumption of PGA and ADC is 8.2mW for each conversion. The whole camera chip reaches 10508 frames per second (fps) at full resolution with 3.1mm x 3.4mm area.Dissertation/ThesisMasters Thesis Electrical Engineering 201

A Focal Plane Array and Electronics Model for CMOS and CCD Sensors in the AFIT Sensor and Scene Emulation Tool (ASSET)

Electro-optical and infrared (EO/IR) sensor models are useful tools that can facilitate understanding a system\u27s behavior without expensive and time-consuming testing of an actual system. EO/IR models are especially important to the military industry where truth data is required but is sometimes impractical to obtain through experimentation due to expense or difficulties in procuring hardware. This work describes implementation of a focal plane array (FPA) model of charge-coupled device (CCD) and complementary metal-oxide semiconductor (CMOS) photodetectors as a component in the Air Force Institute of Technology (AFIT) Sensor and Scene Emulation Tool (ASSET). The FPA model covers conversion of photo-generated electrons to voltage and then to digital numbers. It incorporates sense node, source follower, and analog-to-digital converter (ADC) components contributing to gain non-linearities and includes noise sources associated with the detector and electronics such as shot, thermal, 1/f, and quantization noise. This thesis describes the higher fidelity FPA and electronics model recently incorporated into ASSET, and it also details validation of the improved model using EO/IR imager data collected with laboratory measurements. The result is an improved model capable of generating realistic synthetic data representative of a wide range of systems for use in new algorithm development and data exploitation techniques supporting a broad community of academic, commercial, and military researchers

Simulations and Design of a Single-Photon CMOS Imaging Pixel Using Multiple Non-Destructive Signal Sampling

A single-photon CMOS image sensor (CIS) design based on pinned photodiode (PPD) with multiple charge transfers and sampling is described. In the proposed pixel architecture, the photogenerated signal is sampled non-destructively multiple times and the results are averaged. Each signal measurement is statistically independent and by averaging, the electronic readout noise is reduced to a level where single photons can be distinguished reliably. A pixel design using this method was simulated in TCAD and several layouts were generated for a 180-nm CMOS image sensor process. Using simulations, the noise performance of the pixel was determined as a function of the number of samples, sense node capacitance, sampling rate and transistor characteristics. The strengths and limitations of the proposed design are discussed in detail, including the trade-off between noise performance and readout rate and the impact of charge transfer inefficiency (CTI). The projected performance of our first prototype device indicates that single-photon imaging is within reach and could enable ground-breaking performances in many scientific and industrial imaging applications

A Low-Power Capacitive Transimpedance D/A Converter

This thesis proposes a new low-power and low-area DAC for single-slope ADCs used in CMOS image sensors. With increase in resolution requirements for ADCs, conventional DAC architectures suffered the limitation of either large area or high power consumption with higher resolution scaling. Thus, the proposed capacitive transimpedance amplifier DAC (CTIA DAC) could solve this by offering the resolution requirement required without taking a hit on the area or power budget. The thesis has been structured in the following manner: The first chapter introduces image sensors in general and talks about progression through different image sensors and pixel architectures that have been used through the years. It also explains the operation of a CMOS image sensor from a paper published from Sony on high-speed image sensors. The second chapter presents the importance and role of DACs in CMOS image sensors and briefly explains a few commonly used DAC architectures in image sensors. It explains the advantages and disadvantages of present architectures and leads the discussion towards the development of the proposed DAC. The third chapter gives an overview of the CTIA DAC and explains the working of the different circuit blocks that are used to implement the proposed DAC. Chapter Four explains the design approach for the blocks explained in Chapter Three. It presents the critical design choices that were made for overall performance of the DAC. Results of individual blocks and the DAC as a whole are presented and compared against other recently published DAC papers. The final chapter summarizes some key results of the design and talks about the scope for future work and improvement

Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído, rapidez e pouca área utilizada, de forma a obter-se o melhor rácio. Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos de operação, assim como as suas características físicas e suas métricas de avaliação. No seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões, terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto com o possível trabalho futuro

Pixels for focal-plane scale space generation and for high dynamic range imaging

Focal-plane processing allows for parallel processing throughout the entire pixel matrix, which can help increasing the speed of vision systems. The fabrication of circuits inside the pixel matrix increases the pixel pitch and reduces the fill factor, which leads to reduced image quality. To take advantage of the focal-plane processing capabilities and minimize image quality reduction, we first consider the inclusion of only two extra transistors in the pixel, allowing for scale space generation at the focal plane. We assess the conditions in which the proposed circuitry is advantageous. We perform a time and energy analysis of this approach in comparison to a digital solution. Considering that a SAR ADC per column is used and the clock frequency is equal to 5.6 MHz, the proposed analysis show that the focal-plane approach is 26 times faster if the digital solution uses 10 processing elements, and 49 times more energy-efficient. Another way of taking advantage of the focal-plane signal processing capability is by using focal-plane processing for increasing image quality itself, such as in the case of high dynamic range imaging pixels. This work also presents the design and study of a pixel that captures high dynamic range images by sensing the matrix average luminance, and then adjusting the integration time of each pixel according to the global average and to the local value of the pixel. This pixel was implemented considering small structural variations, such as different photodiode sizes for global average luminance measurement. Schematic and post-layout simulations were performed with the implemented pixel using an input image of 76 dB, presenting results with details in both dark and bright image areas.O processamento no plano focal de imageadores permite que a imagem capturada seja processada em paralelo por toda a matrix de pixels, característica que pode aumentar a velocidade de sistemas de visão. Ao fabricar circuitos dentro da matrix de pixels, o tamanho do pixel aumenta e a razão entre área fotossensível e a área total do pixel diminui, reduzindo a qualidade da imagem. Para utilizar as vantagens do processamento no plano focal e minimizar a redução da qualidade da imagem, a primeira parte da tese propõe a inclusão de dois transistores no pixel, o que permite que o espaço de escalas da imagem capturada seja gerado. Nós então avaliamos em quais condições o circuito proposto é vantajoso. Nós analisamos o tempo de processamento e o consumo de energia dessa proposta em comparação com uma solução digital. Utilizando um conversor de aproximações sucessivas com frequência de 5.6 MHz, a análise proposta mostra que a abordagem no plano focal é 26 vezes mais rápida que o circuito digital com 10 elementos de processamento, e consome 49 vezes menos energia. Outra maneira de utilizar processamento no plano focal consiste em aplicá-lo para melhorar a qualidade da imagem, como na captura de imagens em alta faixa dinâmica. Esta tese também apresenta o estudo e projeto de um pixel que realiza a captura de imagens em alta faixa dinâmica através do ajuste do tempo de integração de cada pixel utilizando a iluminação média e o valor do próprio pixel. Esse pixel foi projetado considerando pequenas variações estruturais, como diferentes tamanhos do fotodiodo que realiza a captura do valor de iluminação médio. Simulações de esquemático e pós-layout foram realizadas com o pixel projetado utilizando uma imagem com faixa dinâmica de 76 dB, apresentando resultados com detalhes tanto na parte clara como na parte escura da imagem

A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC

The \emph{MIDNA} application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65 nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm${^2}$ area and has an input referred noise of 2.7${\mu\nu}_{rms}$. It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2${e^{-}}$ RMS by averaging 1000 samples with MIDNA both at room temperature and at 180 Kelvin

High-Speed Radhard Mega-Pixel CIS Camera for High-Energy Physics

This dissertation describes the schematic design, physical layout implementation, system-level hardware with FPGA firmware design, and testing of a camera-on-a-chip with a novel high-speed CMOS image sensor (CIS) architecture developed for a mega-pixel array. The novel features of the design include an innovative quadruple column-parallel readout (QCPRO) scheme with rolling shutter that increases pixel rate, its ability to program the frame rate and to tolerate Total Ionizing Dose effects (TID). Two versions of the architecture, a small (128 x 1,024 pixels) and large (768 x 1,024 pixels) version were designed and fabricated with a custom layout that does not include library parts. The designs achieve a performance of 20 to 4,000 frames per second (fps) and they tolerate up to 125 krads of radiation exposure. The high-speed CIS architecture proposes and implements a creative quadruple column-parallel readout (QCPRO) scheme to achieve a maximum pixel rate, 10.485 gigapixels/s. The QCPRO scheme consists of four readout blocks per column and to complete four rows of pixels readout process at one line time. Each column-level readout block includes an analog time-interleaving (ATI) sampling circuit, a switched-capacitor programmable gain amplifier (SC-PGA), a 10-bit successive-approximation register (SAR) ADC, two 10-bit memory banks. The column-parallel SAR ADC is area-efficient to be laid out in half of one pixel pitch, 10 um. The analog ATI sampling circuit has two sample-and-hold circuits. Each sampling circuit can independently complete correlated double sampling (CDS) operation. Furthermore, to deliver over 10^10 pixel data in one second, a high-speed differential Scalable Low-Voltage Signaling (SLVS) transmitter for every 16 columns is designed to have 1 Gbps/ch at 0.4 V. Two memory banks provide a ping-pong operation: one connecting to the ADC for storing digital data and the other to the SLVS for delivering data to the off-chip FPGA. Therefore, the proposed CIS architecture can achieve 10,000 frames per second for a 1,024 x 1,024 pixel array. The floor plan of the proposed CIS architecture is symmetrical having one-half of pixel rows to read out on top, and the other half read out on the bottom of the pixel array. The rolling shutter feature with multi-lines readout in parallel and oversampling technique relaxes the image artifacts for capturing fast-moving objects. The CIS camera can provide complete digital input control and digital pixel data output. Many other components are designed and integrated into the proposed CMOS imager, including the Serial Peripheral Interface (SPI), bandgap reference, serializers, phase-locked loops (PLLs), and sequencers with configuration registers. Also, the proposed CIS can program the frame rate for wider applications by modifying three parameters: input clock frequency, the region of interest, and the counter size in the sequencer. The radiation hardening feature is achieved by using the combination of enclosed geometry technique and P-type guard-rings in the 0.18 um CMOS technology. The peripheral circuits use P-type guard-rings to cut the TID-induced leakage path between device to device. Each pixel cell is radiation tolerant by using enclosed layout transistors. The pinned photodiode is also used to get low dark current, and correlated double sampling to suppress pixel-level fixed-pattern noise and reset noise. The final pixel cell is laid out in 20 x 20 um^2. The total area of the pixel array is 2.56 x 20.28 mm^2 for low-resolution imager prototype and 15.36 x 20.28 mm^2 for high-resolution imager prototype. The entire CIS camera system is developed by the implementation of the hardware and FPGA firmware of the small-format prototype with 128 x 1,024 pixels and 754 pads in a 4.24 x 25.125 mm^2 die area. Different testing methods are also briefly described for different test purposes. Measurement results validate the functionalities of the readout path, sequencer, on-chip PLLs, and the SLVS transmitters. The programmable frame rate feature is also demonstrated by checking the digital control outputs from the sequencer at different frame rates. Furthermore, TID radiation tests proved the pixels can work under 125 krads radiation exposure