Update - Body of Knowledge (BOK) for Copper Wire Bonds

Copper wire bond technology developments continue to be a subject of technical interest to the NASA (National Aeronautics and Space Administration) NEPP (NASA Electronic Parts and Packaging Program) which funded this update. Based on this new research, additional copper bond wire vulnerabilities were found in the literature - Crevice corrosion, intrinsic degradation of palladium coated copper wire, congregation of palladium near ball bond interface leading to failure, residual aluminum pad metallization impact on device lifetimes, stitch cracking phenomena, package delamination's that have resulted in wire bond failures and device failure due to elemental sulfur. A search of the U.S.A. patent web site found 3 noteworthy patents on the following developments: claim of a certain IMC (Intermetallic Compound) thickness as a mitigation solution to chlorine corrosion; claim of using materials with different pHs to neutralize contaminants in a package containing copper wire bonds; and a discussion on ball shear test threshold values for different applications. In addition, an aerospace contractor of military hardware had a presentation on copper bond wires where it was reported that there was a parametric shift and noise susceptibility of devices with copper bond wires which affected legacy design performance. A review of silver bond wire (another emerging technology) technical papers found that an electromigration failure mechanism was evident in device applications that operate under high current conditions. More studies may need to be performed on a comprehensive basis. Research areas for consideration are suggested, however, these research and or qualification/standard test areas are not all inclusive and should not be construed as the element (s) that delivers any potential copper wire bond solution. A false sense of security may occur, whenever there is a reliance on passing any particular qualification, standard, or test protocol

Body of Knowledge (BOK) for Copper Wire Bonds

Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate - approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling. Despite the difficult problems associated with the changeover to copper bonding wire, there are billions of copper wire bonded devices delivered annually to customers. It is noteworthy that Texas Instruments announced in October of 2014 that they are shipping microcircuits containing copper wire bonds for safety critical automotive applications. An evaluation of copper wire bond technology for applicability to spaceflight hardware may be warranted along with concurrently compiling a comprehensive understanding of the failure mechanisms involved with copper wire bonded semiconductor devices

Selective electroless nickel deposition on copper as a final barrier/bonding layer material for microelectronics applications

A low cost, selective electroless metallisation of integrated circuit (IC) copper bond pads with nickel and gold is demonstrated. This metallurgy can function as a barrier layer/bondable material when deposited as a thin layer or as the chip bump for flip chip applications when deposited to greater heights. Four alternative activation steps for selective electroless nickel deposition on bond pad copper are demonstrated. Selective low cost deposition has been achieved with a proprietary electroless plating bath developed at NMRC and three commercial baths on both sputtered copper substrates and electrolessly deposited copper on titanium nitride barrier layer material

Design, processing and testing of LSI arrays hybrid microelectronics task

Those factors affecting the cost of electronic subsystems utilizing LSI microcircuits were determined and the most efficient methods for low cost packaging of LSI devices as a function of density and reliability were developed

Beam lead technology

Beam lead technology for microcircuit interconnections with applications to metallization, passivation, and bondin

Environmentally Sustainable Solvent-based Process Chemistry for Metals in Printed Circuit Boards

This chapter describes the development of several new processes relating to the fabrication, characterisation and recycling of printed circuit board (PCB) metal assemblies in alternative, sustainable solvent technologies based on an emergent class of liquids know as deep eutectic solvents (DES). It has been demonstrated that in many cases, the use of DES technologies can be disruptive to current process thinking and in principle can deliver benefits including increased efficiency,lower costs and better process control. These technologies offer the opportunity to incorporate new ideas into PCB fabrication and assembly that facilitate downstream, end-of-life recovery and separation consistent with a circular economy model. Current PCB manufacturing is carried out using many complex metal deposition processes involving aqueous solutions of toxic metal salts, strong inorganic acids, precious and expensive noble metals, and requires careful process control and monitoring. As a result, these processes are often costly to operate and inefficient. DES-based technologies can: (1) improve the economic and efficient use of essential metals; (2) reduce or eliminate use of precious and expensive metals; (3) reduce the use of complex and difficult to maintain process chemistry; (4) reduce reliance on toxic and noxious materials; and (5) improve recovery, recycling and reuse of PCB metals

Development of a solder bump technique for contacting a three-dimensional multi electrode array

The application of a solder bump technique for contacting a three-dimensional multi electrode array is presented. Solder bumping (or C4: Controlled Collapse Chip Connections, also called Flip Chip contacting) is the most suitable contacting technique available for small dimensions and large numbers of connections. Techniques adapted from the literature could successfully be scaled down to be used for 55x55 μm pads at 120 μm heart-to-heart spacing, yielding well-conducting, reasonably strong bonds

All-copper chip-to-substrate interconnects for high performance integrated circuit devices

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.Ph.D.Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, Jame

Entwicklung mikroelektronischer Kontaktierungsmethoden für Hochtemperatur-Anwendungen über 250 °C

Das Hauptziel der vorliegenden Dissertation war die Entwicklung von Methoden zur Herstellung mikroelektronischer Kontakte mit Temperaturstabilitäten über 250 °C unter Verwendung von Flip-Chip-Technologie und Drahtbond-Technologie. In der Drahtbond-Technologie bieten Palladiumdrähte gegenüber standardmäßig verwendeten Golddrähten Vorteile hinsichtlich mechanischer Stabilität und 50 % geringerer Materialkosten. Die vorliegende Arbeit präsentiert eine Studie über das Schweißverhalten von Palladiumdrähten unter Verwendung von Thermosonic-Verfahren auf galvanisch abgeschiedenen Gold-Metallisierungen. Es wurden Zuverlässigkeitsuntersuchungen an Palladiumdraht-Kontakten bis zu Temperaturen von 350 °C durchgeführt. Die mechanische Stabilität wurde durch Schertests und Zugfestigkeitstests geprüft. Zur Untersuchung des Mikrogefüges wurden Drahtbond-Querschnitte mittels Rasterelektronenmikroskopie (REM) analysiert. Ergänzend zur Drahtbond-Technologie wurde eine Methode zur Herstellung hochtemperaturbeständiger Flip-Chip-Kontaktierungen entwickelt. Durch eine Verlötung mit Lötrahmen entlang der Chip-Außenkanten wurde analog zu kommerziellen Flip-Chip-Packages eine Krümmung über das gesamte Flip-Chip-Package generiert. Durch diese Deformation, welche üblicherweise durch die Verwendung von Underfills erzeugt wird, werden thermomechanische Spannungen in den Bumps reduziert. Da die präsentierte Flip-Chip-Methode im Unterschied zu kommerziellen Flip-Chip-Verfahren keine Applikation von Underfill beinhaltet, deren Temperaturbeständigkeit bei maximal 170 °C liegt, können Einsatztemperaturen von mindestens 250 °C realisiert werden. Durch sukzessives elektrochemisches Abscheiden unterschiedlicher Metall-Schichten wurden Bumps und Lötrahmen bestehend aus einem Kupfer/Nickel/Gold/Zinn-Schichtsystem hergestellt. Diese Strukturen wurden durch einen Gold/Zinn-SLID Prozess (Solid-Liquid Interdiffusion) auf Keramiksubstrate verlötet. Mit Hilfe von FEM-Simulationen (Finite Elemente Methode) wurde die Auswirkung der Lötrahmen auf thermomechanische Spannungen in Flip-Chip-Bumps berechnet. Die Krümmung der Flip-Chip-Packages, welche als Validierungsparameter für das FEM-Modell dienten, wurde mit Hilfe optischer Interferometrie bestimmt. Zur experimentellen Untersuchung der Lötverbindungen wurden Querschnittanalysen mittels Raster-Elektronen-Mikroskopie (REM) durchgeführt. Die Zuverlässigkeit der Flip-Chip-Packages wurde durch Widerstandmessungen an Daisy-Chain-Teststrukturen nach Temperaturlagerungen bei 250 °C und Temperaturwechselzyklen zwischen -50 °C bis 175 °C geprüft.The main purpose of the presented doctoral thesis was the development of micro-contacts with a temperature resistance over 250 °C by using flip-chip technology and wire bonding technology. In wire bonding technology palladium wire, in comparison to gold wire, has the advantages of higher mechanical stability and about 50 % lower material costs. This thesis presents a detailed investigation about the process performance of thermosonic palladium wire bonding on electroplated gold metallizations. The reliabilities of the fabricated wire bonds were tested at temperatures up to 350 °C. The mechanic bond stability was determined by wire pull tests and bond shear tests. The microscopic texture of the interfaces between the wire bonds and the bond pads were determined by cross sectional scanning electron microscopy (SEM). Additional to the wire bonding technology also flip-chip technology was used for the fabrication of high temperature resistant interconnects to silicon-dies. Therefore the outer edges of the silicon-dies were contacted by a seal ring, whereby a warpage of the packages was generated similar to commercial flip-chip packages. This deformation, in general generated by the application of underfills, which have a temperature stability of maximum 170 °C, reduces thermomechanical stress in flip-chip bumps. In comparison to commercial flip-chip technology the presented flip-chip method works without the usage of underfills. Thus the fabricated packages can be operated at temperatures up to 250 °C. By the successive electrochemical plating of different metal layers bumps and seal rings consisting of a copper/nickel/gold/tin metal-stack were fabricated. These structures were connected by a high temperature resistant gold/tin-SLID solder process (Solid-Liquid Interdiffusion) to ceramic substrates. The influence of the seal rings to the thermomechanical stress in flip-chip bumps was calculated by FEM-simulations (finite elements method). The warpages of the flip-chip packages were measured by optical interferometry. These data were used for experimental validation of the FEM-model. The solder interface of the flip-chip bumps was determined by sectional scanning electron microscopy (SEM). Reliability tests were performed by permanent temperature load up to 250 °C und thermal cycles between -50 °C and 175 °C. After these loads the functionality of the bump connections was tested by measuring the electric resistance of daisy chain test structures

Bonding and adjoining technology: A compilation

This compilation covers NASA and AEC developed techniques covering bonding, brazing, and joining methods and technology