DSA-aware multiple patterning for the manufacturing of vias: Connections to graph coloring problems, IP formulations, and numerical experiments

In this paper, we investigate the manufacturing of vias in integrated circuits with a new technology combining lithography and Directed Self Assembly (DSA). Optimizing the production time and costs in this new process entails minimizing the number of lithography steps, which constitutes a generalization of graph coloring. We develop integer programming formulations for several variants of interest in the industry, and then study the computational performance of our formulations on true industrial instances. We show that the best integer programming formulation achieves good computational performance, and indicate potential directions to further speed-up computational time and develop exact approaches feasible for production

VLSI Revisited - Revival in Japan

This paper describes the abundance of semiconductor consortia that have come into existence in Japan since the mid-1990s. They clearly reflect the ambition of the government - through its reorganized ministry METI and company initiatives - to regain some of the industrial and technological leadership that Japan has lost. The consortia landscape is very different in Japan compared with EU and the US. Outside Japan the universities play a much bigger and very important role. In Europe there has emerged close collaboration, among national government agencies, companies and the EU Commission in supporting the IT sector with considerable attention to semiconductor technologies. Another major difference, and possibly the most important one, is the fact that US and EU consortia include and mix partners from different areas of the semiconductor landscape including wafer makers, material suppliers, equipment producers and integrated device makers.semiconductors, Hitachi, Sony, Toshiba, Elpida, Renesas, Sematech, VLSI, JESSI, MEDEA, ASPLA, MIRAI, innovation system

Nanomechanical single-photon routing

The merger between integrated photonics and quantum optics promises new opportunities within photonic quantum technology with the very significant progress on excellent photon-emitter interfaces and advanced optical circuits. A key missing functionality is rapid circuitry reconfigurability that ultimately does not introduce loss or emitter decoherence, and operating at a speed matching the photon generation and quantum memory storage time of the on-chip quantum emitter. This ambitious goal requires entirely new active quantum-photonic devices by extending the traditional approaches to reconfigurability. Here, by merging nano-optomechanics and deterministic photon-emitter interfaces we demonstrate on-chip single-photon routing with low loss, small device footprint, and an intrinsic time response approaching the spin coherence time of solid-state quantum emitters. The device is an essential building block for constructing advanced quantum photonic architectures on-chip, towards, e.g., coherent multi-photon sources, deterministic photon-photon quantum gates, quantum repeater nodes, or scalable quantum networks.Comment: 7 pages, 3 figures, supplementary informatio