Modelling and simulation of paradigms for printed circuit board assembly to support the UK's competency in high reliability electronics

The fundamental requirement of the research reported within this thesis is the provision of physical models to enable model based simulation of mainstream printed circuit assembly (PCA) process discrete events for use within to-be-developed (or under development) software tools which codify cause & effects knowledge for use in product and process design optimisation. To support a national competitive advantage in high reliability electronics UK based producers of aircraft electronic subsystems require advanced simulation tools which offer model based guidance. In turn, maximization of manufacturability and minimization of uncontrolled rework must therefore enhance inservice sustainability for ‘power-by-the-hour’ commercial aircraft operation business models. [Continues.

Product Development in the World Auto Industry

macroeconomics, auto industry, management efficiency, productivity

ARMD Workshop on Materials and Methods for Rapid Manufacturing for Commercial and Urban Aviation

This report documents the goals, organization and outcomes of the NASA Aeronautics Research Mission Directorates (ARMD) Materials and Methods for Rapid Manufacturing for Commercial and Urban Aviation Workshop. The workshop began with a series of plenary presentations by leaders in the field of structures and materials, followed by concurrent symposia focused on forecasting the future of various technologies related to rapid manufacturing of metallic materials and polymeric matrix composites, referred to herein as composites. Shortly after the workshop, questionnaires were sent to key workshop participants from the aerospace industry with requests to rank the importance of a series of potential investment areas identified during the workshop. Outcomes from the workshop and subsequent questionnaires are being used as guidance for NASA investments in this important technology area

Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

Advanced RF and Microwave Design Optimization: A Journey and a Vision of Future Trends

In this paper, we outline the historical evolution of RF and microwave design optimization and envisage imminent and future challenges that will be addressed by the next generation of optimization developments. Our journey starts in the 1960s, with the emergence of formal numerical optimization algorithms for circuit design. In our fast historical analysis, we emphasize the last two decades of documented microwave design optimization problems and solutions. From that retrospective, we identify a number of prominent scientific and engineering challenges: 1) the reliable and computationally efficient optimization of highly accurate system-level complex models subject to statistical uncertainty and varying operating or environmental conditions; 2) the computationally-efficient EM-driven multi-objective design optimization in high-dimensional design spaces including categorical, conditional, or combinatorial variables; and 3) the manufacturability assessment, statistical design, and yield optimization of high-frequency structures based on high-fidelity multi-physical representations. To address these major challenges, we venture into the development of sophisticated optimization approaches, exploiting confined and dimensionally reduced surrogate vehicles, automated feature-engineering-based optimization, and formal cognition-driven space mapping approaches, assisted by Bayesian and machine learning techniques.ITESO, A.C

Designing for rapid manufacture

Thesis (M. Tech.) -- Central University of Technology, Free State, 2008As the tendency to use sol id freeform fabrication (SFF) technology for the manufacture of end use parts grew, so too did the need for a set of general guidelines that would aid designers with designs aimed specifically for rapid manufacture. Unfortunately, the revolutionary additive nature of SFF technology left certain fundamental principles of conventional design for manufacture and assembly outdated. This implied that whole chapters of theoretical work that had previously been done in this field had to be revised before it could be applied to rapid manufacturing. Furthermore, this additive nature of SFF technology seeded a series of new possibilities and new advantages that could be exploited in the manufacturing domain, and as a result drove design for rapid manufacturing principles even further apart from conventional design for manufacture and assembly philosophy. In this study the impact that rapid manufacture had on the conventional product development process and conventional design for manufacture and assembly guidelines were investigated. This investigation brought to light the inherent strengths and weaknesses of SFF, as well as the design for manufacture and assembly guidelines that became invalid, and consequently lead directly to the characterization of a set of design for rapid manufacture guidelines

Automatic constraint-based synthesis of non-uniform rational B-spline surfaces

In this dissertation a technique for the synthesis of sculptured surface models subject to several constraints based on design and manufacturability requirements is presented. A design environment is specified as a collection of polyhedral models which represent components in the vicinity of the surface to be designed, or regions which the surface should avoid. Non-uniform rational B-splines (NURBS) are used for surface representation, and the control point locations are the design variables. For some problems the NURBS surface knots and/or weights are included as additional design variables. The primary functional constraint is a proximity metric which induces the surface to avoid a tolerance envelope around each component. Other functional constraints include: an area/arc-length constraint to counteract the expansion effect of the proximity constraint, orthogonality and parametric flow constraints (to maintain consistent surface topology and improve machinability of the surface), and local constraints on surface derivatives to exploit part symmetry. In addition, constraints based on surface curvatures may be incorporated to enhance machinability and induce the synthesis of developable surfaces;The surface synthesis problem is formulated as an optimization problem. Traditional optimization techniques such as quasi-Newton, Nelder-Mead simplex and conjugate gradient, yield only locally good surface models. Consequently, simulated annealing (SA), a global optimization technique is implemented. SA successfully synthesizes several highly multimodal surface models where the traditional optimization methods failed. Results indicate that this technique has potential applications as a conceptual design tool supporting concurrent product and process development methods

Nasics: A `Fabric-Centric\u27 Approach Towards Integrated Nanosystems

This dissertation addresses the fundamental problem of how to build computing systems for the nanoscale. With CMOS reaching fundamental limits, emerging nanomaterials such as semiconductor nanowires, carbon nanotubes, graphene etc. have been proposed as promising alternatives. However, nanoelectronics research has largely focused on a `device-first\u27 mindset without adequately addressing system-level capabilities, challenges for integration and scalable assembly. In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, inter-connection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the `fabric-centric\u27 mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS. We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below

Asynchronous nanowire crossbar architecture for manufacturability, modularity and robustness

This thesis spotlights the dawn of a promising new nanowire crossbar architecture, the Asynchronous crossbar architecture, in the form of three different articles. It combines the reduced size of the nanowire crossbar architecture with the clock-free nature of Null Conventional Logic, which are the primary advantages. The first paper explains the proposed architecture with illustrations, including the design of an optimized full adder. This architecture has an elementary structure termed as a Programmable Gate Macro Block (PGMB) which is analogous to a threshold gate in NCL. The other two papers concentrate on mapping and placement techniques which are important due to defects involved in crossbars. These defects have to be tolerated and logic has to be routed appropriately for successful functioning of the circuit --Introduction, page 1