Two-dimensional DCT/IDCT architecture

A fully parallel architecture for the computation of a two-dimensional (2-D) discrete cosine transform (DCT), based on row-column decomposition is presented. It uses the same one dimensional (1-D) DCT unit for the row and column computations and (N2+N) registers to perform the transposition. It possesses features of regularity and modularity, and is thus well suited for VLSI implementation. It can be used for the computation of either the forward or the inverse 2-D DCT. Each 1-D DCT unit uses N fully parallel vector inner product (VIP) units. The design of the VIP units is based on a systematic design methodology using radix-2” arithmetic, which allows partitioning of the elements of each vector into small groups. Array multipliers without the final adder are used to produce the different partial product terms. This allows a more efficient use of 4:2 compressors for the accumulation of the products in the intermediate stages and reduces the number of accumulators from N to one. Using this procedure, the 2-D DCT architecture requires less than N2 multipliers (in terms of area occupied) and only 2N adders. It can compute a N x N-point DCT at a rate of one complete transform per N cycles after an appropriate initial delay

Efficient hardware architectures for MPEG-4 core profile

Efficient hardware acceleration architectures are proposed for the most demandingMPEG-4 core profile algorithms, namely; texture motion estimation (TME), binary motion estimation (BME)and the shape adaptive discrete cosine transform (SA-DCT). The proposed ME designs may also be used for H.264, since both architectures can handle variable block sizes. Both ME architectures employ early termination techniques that reduce latency and save needless memory accesses and power consumption. They also use a pixel subsampling technique to facilitate parallelism, while balancing the computational load. The BME datapath also saves operations by using Run Length Coded (RLC) pixel addressing. The SA-DCT module has a re-configuring multiplier-less serial datapath using adders and multiplexers only to improve area and power. The SA-DCT packing steps are done using a minimal switching addressing scheme with guarded evaluation. All three modules have been synthesised targeting the WildCard-II FPGA benchmarking platform adopted by the MPEG-4 Part9 reference hardware group

Number theoretic techniques applied to algorithms and architectures for digital signal processing

Many of the techniques for the computation of a two-dimensional convolution of a small fixed window with a picture are reviewed. It is demonstrated that Winograd's cyclic convolution and Fourier Transform Algorithms, together with Nussbaumer's two-dimensional cyclic convolution algorithms, have a common general form. Many of these algorithms use the theoretical minimum number of general multiplications. A novel implementation of these algorithms is proposed which is based upon one-bit systolic arrays. These systolic arrays are networks of identical cells with each cell sharing a common control and timing function. Each cell is only connected to its nearest neighbours. These are all attractive features for implementation using Very Large Scale Integration (VLSI). The throughput rate is only limited by the time to perform a one-bit full addition. In order to assess the usefulness to these systolic arrays a 'cost function' is developed to compare them with more conventional techniques, such as the Cooley-Tukey radix-2 Fast Fourier Transform (FFT). The cost function shows that these systolic arrays offer a good way of implementing the Discrete Fourier Transform for transforms up to about 30 points in length. The cost function is a general tool and allows comparisons to be made between different implementations of the same algorithm and between dissimilar algorithms. Finally a technique is developed for the derivation of Discrete Cosine Transform (DCT) algorithms from the Winograd Fourier Transform Algorithm. These DCT algorithms may be implemented by modified versions of the systolic arrays proposed earlier, but requiring half the number of cells

A novel approach to fast discrete Hartley transform

The Discrete Hartley transform (DHT) is an important tool in digital signal processing. We propose a novel approach to perform DHT. We transform DHT into a form expressed in discrete moments via a modular mapping and truncating Taylor series expansion and present a completely new formula for computing DHT. We extend the use of our systolic array for fast computation of moments without any multiplications, to one that computes DHT with only a few multiplications and without any evaluations of triangular functions. The multiplication number used in our method is O(Nlog2N/log2log2N) superior to O(Nlog 2N) in the conventional FDT. The execution time of the systolic array is only O(Nlog2N/log2log2N) for 1-D DHT and O(N k) for k-D DHT (k⩾2). The systolic array consists of very simple processing elements and hence it implies an easy and potential hardware/VLSI implementation. The approach is also applicable to DHT inverses.published_or_final_versio

Data compression techniques applied to high resolution high frame rate video technology

An investigation is presented of video data compression applied to microgravity space experiments using High Resolution High Frame Rate Video Technology (HHVT). An extensive survey of methods of video data compression, described in the open literature, was conducted. The survey examines compression methods employing digital computing. The results of the survey are presented. They include a description of each method and assessment of image degradation and video data parameters. An assessment is made of present and near term future technology for implementation of video data compression in high speed imaging system. Results of the assessment are discussed and summarized. The results of a study of a baseline HHVT video system, and approaches for implementation of video data compression, are presented. Case studies of three microgravity experiments are presented and specific compression techniques and implementations are recommended

Improved approximate QR-LS algorithms for adaptive filtering

This paper studies a class of O(N) approximate QR-based least squares (A-QR-LS) algorithm recently proposed by Liu in 1995. It is shown that the A-QR-LS algorithm is equivalent to a normalized LMS algorithm with time-varying stepsizes and element-wise normalization of the input signal vector. It reduces to the QR-LMS algorithm proposed by Liu et al. in 1998, when all the normalization constants are chosen as the Euclidean norm of the input signal vector. An improved transform-domain approximate QR-LS (TA-QR-LS) algorithm, where the input signal vector is first approximately decorrelated by some unitary transformations before the normalization, is proposed to improve its convergence for highly correlated signals. The mean weight vectors of the algorithms are shown to converge to the optimal Wiener solution if the weighting factor w of the algorithm is chosen between 0 and 1. New Givens rotations-based algorithms for the A-QR-LS, TA-QR-LS, and the QR-LMS algorithms are proposed to reduce their arithmetic complexities. This reduces the arithmetic complexity by a factor of 2, and allows square root-free versions of the algorithms be developed. The performances of the various algorithms are evaluated through computer simulation of a system identification problem and an acoustic echo canceller. © 2004 IEEE.published_or_final_versio

On the realization of discrete cosine transform using the distributed arithmetic

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Kemahiran boleh pindah dalam kalangan pelajar kejuruteraan di IPTA

Kemahiran boleh pindah didefinisikan sebagai kemahiran yang dimiliki oleh individu yang mempunyai kepelbagaian pengetahuan, nilai-nilai serta kemahiran hidup asas (life skills) yang diperlukan demi mendapatkan dan mengekalkan pekerjaan sedia ada. Kajian berbentuk tinjauan kuantitatif ini bertujuan untuk mengenal pasti persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya dari aspek adaptif, pemikiran kritis dan penyelesaian masalah. Di samping itu, kajian ini juga bertujuan untuk mengenal pasti perbezaan persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan perbezaan terhadap tahap penguasaannya di antara lelaki dan perempuan. Seramai 297 orang pelajar kejuruteraan tahun tiga lepasan matrikulasi Universiti Tun Hussein Onn Malaysia telah terpilih sebagai responden untuk menjawab borang soal selidik. Data dianalisis dengan mencari nilai skor min dan Ujian-t tidak bersandar menggunakan perisian Statistical Package for Social Science (SPSS). Dapatan kajian menunjukkan bahawa persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya berada pada tahap tinggi dengan nilai skor min 4.0864 dan 4.0282. Kajian juga menunjukkan bahawa wujudnya perbezaan yang signifikan dalam skor min persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah antara lelaki dan perempuan dengan nilai t signifikan 0.003. Namun begitu, hasil analisis menunjukkan tiada perbezaan bagi tahap penguasaannya dengan nilai t signifikan 0.327. Secara keseluruhannya, kesedaran yang tinggi akan membantu pelajar untuk menguasai keseluruhan kemahiran dengan sempurna. Ia juga boleh dijadikan panduan bagi pelajar untuk mengenal pasti elemen dan ciri-ciri yang diperlukan oleh majikan pada masa kini