Design methodology for behavioral surface roughness modeling and high-speed test board design

A behavioral model is introduced, which can predict low-loss and low surface roughness transmission line time- and frequency- domain performances. High data rates push for better performance of PCB transmission lines. However, the roughness of copper foil has a considerable impact on the signal integrity performance of transmission lines at high data rates and long propagation distance. Existing models for low-loss transmission line surface roughness are inadequate. A new behavioral model to represent the surface roughness has been developed. The model is applied in the design process by adding a dispersive term to the bulk dielectric permittivity to represent the loss due to the foil surface roughness. By adding a broadband dielectric model into original transmission model, time- and frequency-domain performance improvements is achieved. Two version of high-speed PCB test board via-transition design optimization is presented, the goal is to make the working frequency up to 50GHz and also will summarize a design flow for design a high-speed board with single and differential signal traces --Abstract, page iii

Robust simulation methodology for surface-roughness loss in interconnect and package modelings

In multigigahertz integrated-circuit design, the extra energy loss caused by conductor surface roughness in metallic interconnects and packagings is more evident than ever before and demands explicit consideration for accurate prediction of signal integrity and energy consumption. Existing techniques based on analytical approximation, despite simple formulations, suffer from restrictive valid ranges, namely, either small or large roughness/frequencies. In this paper, we propose a robust and efficient numerical-simulation methodology applicable to evaluating general surface roughness, described by parameterized stochastic processes, across a wide frequency band. Traditional computation-intensive electromagnetic simulation is avoided via a tailored scalar-wave modeling to capture the power loss due to surface roughness. The spectral stochastic collocation method is applied to construct the complete statistical model. Comparisons with full wave simulation as well as existing methods in their respective valid ranges then verify the effectiveness of the proposed approach. © 2009 IEEE.published_or_final_versio

Measurements and simulation of conductor-related loss of PCB transmission lines

With continuously increasing data rates Signal Integrity (SI) problems become more and more challenging. One of the main issues in high-speed data transfer is the frequency-dependent loss of transmission lines. This thesis is dedicated to conductor-related loss mechanisms in printed circuit board (PCB) transmission lines. This thesis provides the experimental investigation of conductor properties used for fabrication of PCBs. Particularly, the resistivity and conductivity along with the temperature coefficients of eleven copper types is measured and reported. A four probe measurement technique is used. Results were verified by two independent measurements and show discrepancy of less than 0.5%. Another major conductor-related loss mechanism is the attenuation of the electromagnetic waves due to the surface roughness of PCB conductors. There are several models attempting to take into account the roughness effect. However none of them are able to explain or predict the transmission line behavior with high accuracy. Particularly, the experimental observations show that the slope of S21 curves increases with frequency, which cannot be modelled by the existing model. To better understand the physics associated with the loss due to the surface roughness of conductors, and be able to predict the behavior of transmission lines in the future, a full wave model of surface roughness was developed. The detailed methodology for 3D roughness generation is provided --Abstract, page iii

Printing conductive traces to enable high frequency wearable electronics applications

With the emergence of the Internet of Things (IoT), wireless body area networks (WBANs) are becoming increasingly pervasive in everyday life. Most WBANs are currently working at the IEEE 802.15.4 Zigbee standard. However there are growing interests to investigate the performance of BANs operating at higher frequencies (e.g. millimetre-wave band), due to the advantages offered compared to those operating at lower microwave frequencies. This thesis aims to realise printed conductive traces on flexible substrates, targeted for high frequency wearable electronics applications. Specifically, investigations were performed in the areas pertaining to the surface modification of substrates and the electrical performance of printed interconnects. Firstly, a novel methodology was proposed to characterise the dielectric properties of a non-woven fabric (Tyvek) up to 20 GHz. This approach utilised electromagnetic (EM) simulation to improve the analytical equations based on transmission line structures, in order to improve the accuracy of the conductor loss values in the gigahertz range. To reduce the substrate roughness, an UV-curable insulator was used to form a planarisation layer on a non-porous substrate via inkjet printing. The results obtained demonstrated the importance of matching the surface energy of the substrate to the ink to minimise the ink de-wetting phenomenon, which was possible within the parameters of heating the platen. Furthermore, the substrate surface roughness was observed to affect the printed line width significantly, and a surface roughness factor was introduced in the equation of Smith et al. to predict the printed line width on a substrate with non-negligible surface roughness (Ra ≤ 1 µm). Silver ink de-wetting was observed when overprinting silver onto the UV-cured insulator, and studies were performed to investigate the conditions for achieving electrically conductive traces using commercial ink formulations, where the curing equipment may be non-optimal. In particular, different techniques were used to characterise the samples at different stages in order to evaluate the surface properties and printability, and to ascertain if measurable resistances could be predicted. Following the results obtained, it was demonstrated that measurable resistance could be obtained for samples cured under an ambient atmosphere, which was verified on Tyvek samples. Lastly, a methodology was proposed to model for the non-ideal characteristics of printed transmission lines to predict the high frequency electrical performance of those structures. The methodology was validated on transmission line structures of different lengths up to 30 GHz, where a good correlation was obtained between simulation and measurement results. Furthermore, the results obtained demonstrate the significance of the paste levelling effect on the extracted DC conductivity values, and the need for accurate DC conductivity values in the modelling of printed interconnects

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Skin-Effect Loss Models for Time- and Frequency-Domain PEEC Solver

published_or_final_versio

Modal based BGA modeling in high-speed package

In the Section 1, the improved Root-Omega method for extracting dielectric properties from fabricated multilayer printed circuit boards is proposed. Based on the electrical properties of fabricated transmission lines, the improved Root-Omega method applied to cases with smooth and rough conductors is validated using simulations. Error sensitivity analysis is performed to demonstrate the potential errors in the original Root-Omega procedure and the error sensitivity is significantly reduced by the proposed improvements. In the Section 2, a fast modal-based approach is developed to accurately and efficiently capture the proximity effect. Image theory is also applied in the proposed approach to reduce the computational domain from 3D structure to 2D. The matrix reduction approach is applied to obtain the physical loop inductance. The lumped capacitance is obtained. A π topology equivalent circuit model for the BGA structure is built. Good agreement between the equivalent circuit model and full wave simulation can be achieved up to 40GHz. In the Section 3, the proximity effect for BGAs between parallel plates is carefully considered. A modal-based cavity method is proposed to extract the partial inductance of two parallel plates. The modal basis function is used to count for the non-uniformly distributed current density. The physical loop inductance is further obtained from the matrix reduction approach. The extracted physical loop inductance is validated with a commercial finite element method-based tool. The boundary effect is demonstrated in the inductance extraction. The proposed method is used to optimize for the power distributed network design --Abstract, page iii

Enabling Technologies for 3D ICs: TSV Modeling and Analysis

Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation

Improved attenuation and crosstalk modeling techniques for high-speed channels

”As digital systems are moving in the direction of faster data transmission rate and higher density of circuits, the problem of the far-end crosstalk (FEXT) and frequency-dependent attenuation are becoming the major factors that limit signal integrity performance. This research is focusing on providing several more comprehensive and accurate modeling approaches for striplines on fabricated printed circuit board (PCB). By characterizing the dielectric permittivity of prepreg and core, dielectric loss tangent, and copper foil surface roughness using measurement data, a better agreement between the stripline model and measurement is achieved. First, a method is proposed to extract dielectric loss tangent using coupled striplines’ measured S-parameters and cross-section geometry. By relating modal attenuation factors to the ratio between the differential and common mode per-unit-length resistances, the unknwon surface roughness contribution is eliminated and the contributions of dielectric and conductor loss are separated. In addition, an improved surface roughness modeling approach is proposed by analyzing the microscopical cross-sectional image of the stripline. By combining the characterized surface roughness information and the extracted dielectric properties, the modeled attenuation factor is match with the measurement data. At last, an approach is introduced to extract the dielectric permittivity of prepreg and core. Using known cross-sectional geometry and measured phase of the coupled stirplines under test, the capacitance components in prepreg and core are separated using 2D solver models. Using the stripline model with inhomogeneous dielectric material, more accurate FEXT modeling results are obtained”--Abstract, page iv

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity