FPGA implementation of Reed Solomon codec for 40Gbps Forward Error Correction in optical networks

Reed-Solomon error correcting codes (RS codes) are widely used in communication and data storage systems to recover data from possible errors that occur during data transfer. A growing application of RS codes is Forward Error Correction (FEC) in the Optical Network (OTN G.709), which uses RS(255,239) to support the OTU-3 (43.018 Gbps) standard. There have been considerable efforts in the area of RS architecture for ASIC implementation. However, there appears to be little reported work on efficient RS codec (encoder and decoder) for Field Programmable Gate Arrays (FPGAs), which has increasing interests in industry. This thesis investigates the implementation and design methodology of the RS(255,239) codec on FPGAs. A portable VHDL code is developed and synthesized for Xilinx\u27s Virtex4 and Altera\u27s StratixII. The FPGA architectures are analyzed and the required design methodologies are adopted to efficiently utilize the available resources. Unfortunately, due to the fixed size of FPGA devices, the RS decoder is not only constrained by the required timing of the system, but also by the size of the targeted device. This research will facilitate the decision-making process for selecting a reconfigurable device for a RS decoder, implementing the Berlekamp-Massey Algorithm

PERFORMANCE COMPARISON OF NON-INTERLEAVED BCH CODES AND INTERLEAVED BCH CODES

This project covers the research about the BCH error correcting codes and the performance of interleaved and non-interleaved BCH codes. Both long and short BCH codes for multimedia communication are examined in an A WGN channel. Algorithm for simulating the BCH codes was also being investigated, which includes generating the parity check matrix, generating the message code in Galois array matrix, encoding the message blocks, modulation and decoding the message blocks. Algorithm for interleaving that includes interleaving message, including burst errors and deinterleaving message is combined with the BCH codes algorithm for simulating the interleaved BCH codes. The performance and feasibility of the coding structure are tested. The performance comparison between interleaved and noninterleaved BCH codes is studied in terms of error performance, channel performance and effect of data rates on the bit error rate (BER). The Berlekamp-Massey Algorithm decoding scheme was implemented. Random integers are generated and encoded with BCH encoder. Burst errors are added before the message is interleaved, then enter modulation and channel simulation. Interleaved message is then compared with noninterleaved message and the error statistics are compared. Initially, certain amount of burst errors is used. "ft is found that the graph does not agree with the theoretical bit error rate (BER) versus signal-to-noise ratio (SNR). When compared between each BCH codeword (i.e. n = 31, n = 63 and n = 127), n = 31 shows the highest BER while n = 127 shows the lowest BER. This happened because of the occurrence of error bursts and also due to error frequency. A reduced size or errors from previous is used in the algorithm. A graph similar to the theoretical BER vs SNR is obtained for both interleaved and non-interleaved BCH codes. It is found that BER of non-interleaved is higher than interleaved BCH codes as SNR increases. These observations show that size of errors influence the effect of interleaving. Simulation time is also studied in terms of block length. It is found that interleaved BCH codes consume longer simulation time compared to non-interleaved BCH codes due to additional algorithm for the interleaved BCH codes

Area Reduction Of Syndrome Calculator For Strong Bose-Chaudhuri-Hocquenghem Decoder

Bose–Chaudhuri–Hocquenghem (BCH) codes have a widespread use to provide the error protection for multiple random errors in a binary code. BCH codes is commonly applied in various practical application such as advanced solid-state drives (SSDs), high-speed fiber optical communications system and wireless communication system. The operation in a BCH decoder can be summarized into 3 steps: 1) compute the syndromes from the received codeword; 2) computing the error locator polynomial; 3) locating the errors. This research project proposed an area efficient Syndrome Calculator block of the BCH (n=255, k=111, t=18) decoder. In the previous SC block architecture, all the odd-index syndromes need to be computed by direct calculation which consume more area. In the current proposed architecture, Galois field’s property is exploited to compute the odd-index syndromes by using power operation in order to save the area consumption. This architecture is better in terms of area compared with previous architecture. In conclusion, by computing the odd-index syndromes with power operation, 8% area saving is achieved without compromising the power consumption and its operating frequency