Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

Advanced Integration of Devices Enabled by Laser Crystallization of Silicon

The push for higher levels of performance drives research and innovation in all areas of electronics. Thus far, shrinking circuit sizes and development of new material systems have satisfied this need. Continued scaling and material improvements have become increasingly difficult; simultaneously, more functionality is needed in smaller spaces. Advanced integration techniques provide a solution by engineering together previously incompatible systems. The fabrication of high-performance devices typically requires high temperature processing steps. Since fabrication occurs sequentially, the high temperature prevents the direct integration of two high-performance layers, as completed devices cannot withstand the processing temperatures of subsequent steps. There are significant challenges to integrating process-incompatible systems, and techniques such as wafer bonding, heteroepitaxial growth, and various thin film technologies have shown limited success. In this work, advanced integration is achieved through laser crystallization processes. Unique to laser methods is the ability to locally heat the surface of a material while keeping the underlying substrate at room temperature. This property allows for high performance electronic materials to be integrated with substrates of different functionalities. This thesis focuses on three key components for advanced integration: 1. Laser-crystallized electronic devices, 2. Relevant substrates for integration, and 3. The feasibility of integrating of laser-crystallized devices with low-temperature substrates. Two types of laser-crystallized devices are explored. Thin-film, laser-crystallized silicon transistors are fabricated at low-temperatures and exhibit high mobilities above 400 cm2 2/Vs. Vertical structure diodes built from laser-crystallized silicon outperformed epitaxially-grown diodes of the same geometry. Light emitting diode (LED) arrays are fabricated from compound semiconductor substrates and tested for display applications. These LED arrays are envisioned to sit underneath the laser-crystallized devices, enabling new applications where both high brightness and high performance transistors are needed. Substrates of low-κ dielectric material are also of interest, as they are widely used for their low capacitance properties. Preliminary results suggest that laser crystallization of silicon can be successfully performed on a low-κ dielectric. In addition to enabling new device architectures, it is important for laser crystallization methods to leave the underlying layers unaffected. Simulations of the laser irradiation process predict substrate temperatures to reach only 70C even when the surface reaches the melting temperature of silicon (1400C). Integration feasibility is further investigated with measurements on conventional front-end field effect transistors. When comparing properties from wafers with and without laser processing, no changes in transistor characteristics are observed. In all three components of work, proof-of-principle devices and concepts lay out the groundwork for future investigation. The developed technologies have promising applications in both the microelectronics and display industry. In particular, the integration of LEDs and laser-crystallized silicon enables a high-brightness microdisplay platform for head-mounted displays, pico projectors, and head-up displays

Intermetallic Bonding for High-Temperature Microelectronics and Microsystems: Solid-Liquid Interdiffusion Bonding

Solid-liquid interdiffusion (SLID) bonding for microelectronics and microsystems is a bonding technique relying on intermetallics. The high-melting temperature of intermetallics allows for system operation at far higher temperatures than what solder-bonded systems can do, while still using similar process temperatures as in common solder processes. Additional benefits of SLID bonding are possibilities of fine-pitch bonding, as well as thin-layer metallurgical bonding. Our group has worked on a number of SLID metal systems. We have optimized wafer-level Cu-Sn SLID bonding to become an industrially feasible process, and we have verified the reliability of Au-Sn SLID bonding in a thermally mismatched system, as well as determined the actual phases present in an Au-Sn SLID bond. We have demonstrated SLID bonding for very high temperatures (Ni-Sn, having intermetallics with melting points up to 1280°C), as well as SLID with low process temperatures (Au-In, processed at 180°C, and Au-In-Bi, processed at 90–115°C). We have verified experimentally the high-temperature stability for our systems, with quantified strength at temperatures up to 300°C for three of the systems: Cu-Sn, Au-Sn and Au-In

US Microelectronics Packaging Ecosystem: Challenges and Opportunities

The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technological solutions to enhance cost-effectiveness while incorporating more features into the silicon footprint. One promising approach is Heterogeneous Integration (HI), which involves advanced packaging techniques to integrate independently designed and manufactured components using the most suitable process technology. However, adopting HI introduces design and security challenges. To enable HI, research and development of advanced packaging is crucial. The existing research raises the possible security threats in the advanced packaging supply chain, as most of the Outsourced Semiconductor Assembly and Test (OSAT) facilities/vendors are offshore. To deal with the increasing demand for semiconductors and to ensure a secure semiconductor supply chain, there are sizable efforts from the United States (US) government to bring semiconductor fabrication facilities onshore. However, the US-based advanced packaging capabilities must also be ramped up to fully realize the vision of establishing a secure, efficient, resilient semiconductor supply chain. Our effort was motivated to identify the possible bottlenecks and weak links in the advanced packaging supply chain based in the US.Comment: 22 pages, 8 figure

Physical Aspects of VLSI Design with a Focus on Three-Dimensional Integrated Circuit Applications

This work is on three-dimensional integration (3DI), and physical problems and aspects of VLSI design. Miniaturization and highly complex integrated systems in microelectronics have led to the 3DI development as a promising technological approach. 3DI offers numerous advantages: Size, power consumption, hybrid integration etc., with more thermal problems and physical complexity as trade-offs. We open this work by presenting the design and testing of an example 3DI system, to our knowledge the first self-powering system in a three-dimensional SOI technology. The system uses ambient optical energy harvested by a photodiode array and stored in an integrated capacitor. An on-chip metal interconnect network, beyond its designed role, behaves as a parasitic load vulnerable to electromagnetic coupling. We have developed a spatially-dependent, transient Green's Function based method of calculating the response of an interconnect network to noise. This efficient method can model network delays and noise sensitivity, which are involved problems in both planar and especially in 3DICs. Three-dimensional systems are more susceptible to thermal problems, which also affect VLSI with high power densities, of complex systems and under extreme temperatures. We analytically and experimentally investigate thermal effects in ICs. We study the effects of non-uniform, non-isotropic thermal conductivity of the typically complex IC material system, with a simulator we developed including this complexity. Through our simulations, verified by experiments, we propose a method of cooling or directionally heating IC regions. 3DICs are suited for developing wireless sensor networks, commonly referred to as ``smart dust.'' The ideal smart dust node includes RF communication circuits with on-chip passive components. We present an experimental study of on-chip inductors and transformers as integrated passives. We also demonstrate the performance improvement in 3DI with its lower capacitive loads. 3DI technology is just one example of the intense development in today's electronics, which maintains the need for educational methods to assist student recruitment into technology, to prepare students for a demanding technological landscape, and to raise societal awareness of technology. We conclude this work by presenting three electrical engineering curricula we designed and implemented, targeting these needs among others

A Dry Etch Approach To Reduce Roughness And Eliminate Visible Grind Marks In Silicon Wafers Post Back-grind

3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6nm is demonstrated. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where they are falsely identified as defects. The quality of the surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification followed by a roughness reduction in an iterative manner to produce a smooth surface without visible grind marks post processing

Une méthode d'alignement passive pour le collage de surfaces planes utilisant le squeeze flow

Afin de répondre aux besoins d’assemblage par collage d’une interface optoélectronique, une méthode de positionnement passive a été développée. Cette méthode présente la particularité de ne pas nécessiter de contact mécanique entre les pièces mais utilise le champ de pression généré entre elles, dans l’adhésif lors du collage, pour corriger leur parallélisme. Pour cela, une étude de l’écoulement d’un fluide pressé entre deux plaques a été menée, d’abord analytiquement, puis par la méthode des éléments finis. Cette étude a permis de déterminer les efforts qui s’exercent sur les surfaces des plaques lors du collage et qui peuvent être utilisés pour corriger leur parallélisme. Ces résultats ont ensuite été utilisés pour concevoir une plateforme d’assemblage capable de s’incliner pour rendre les plaques parallèles. L’instrumentation de cette plateforme permet de mesurer les efforts au cours de l’assemblage. Les essais réalisés ont montré un réalignement des plaques, mais les efforts mesurés se sont avérés inférieurs aux prévisions du modèle éléments finis. Des mesures de rhéologie, réalisées sur le fluide utilisé comme adhésif pour les essais, ont mis en évidence un comportement non- Newtonien de celui-ci à des taux de cisaillement élevés. Ces mesures ont conduit au développement d’un nouveau modèle éléments finis, tenant compte de ce comportement et donnant des résultats plus proches des valeurs expérimentales