A Fully Polynomial-Time Approximation Scheme for Speed Scaling with Sleep State

We study classical deadline-based preemptive scheduling of tasks in a computing environment equipped with both dynamic speed scaling and sleep state capabilities: Each task is specified by a release time, a deadline and a processing volume, and has to be scheduled on a single, speed-scalable processor that is supplied with a sleep state. In the sleep state, the processor consumes no energy, but a constant wake-up cost is required to transition back to the active state. In contrast to speed scaling alone, the addition of a sleep state makes it sometimes beneficial to accelerate the processing of tasks in order to transition the processor to the sleep state for longer amounts of time and incur further energy savings. The goal is to output a feasible schedule that minimizes the energy consumption. Since the introduction of the problem by Irani et al. [16], its exact computational complexity has been repeatedly posed as an open question (see e.g. [2,8,15]). The currently best known upper and lower bounds are a 4/3-approximation algorithm and NP-hardness due to [2] and [2,17], respectively. We close the aforementioned gap between the upper and lower bound on the computational complexity of speed scaling with sleep state by presenting a fully polynomial-time approximation scheme for the problem. The scheme is based on a transformation to a non-preemptive variant of the problem, and a discretization that exploits a carefully defined lexicographical ordering among schedules

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Energy Efficiency and Renewable Energy Management with Multi-State Power-Down Systems

A power-down system has an on-state, an off-state, and a finite or infinite number of intermediate states. In the off-state, the system uses no energy and in the on-state energy it is used fully. Intermediate states consume only some fraction of energy but switching back to the on-state comes at a cost. Previous work has mainly focused on asymptotic results for systems with a large number of states. In contrast, the authors study problems with a few states as well as systems with one continuous state. Such systems play a role in energy-efficiency for information technology but are especially important in the management of renewable energy. The authors analyze power-down problems in the framework of online competitive analysis as to obtain performance guarantees in the absence of reliable forecasting. In a discrete case, the authors give detailed results for the case of three and five states, which corresponds to a system with on-off states and three additional intermediate states “power save”, “suspend”, and “hibernate”. The authors use a novel balancing technique to obtain optimally competitive solutions. With this, the authors show that the overall best competitive ratio for three-state systems is 95 role= presentation style= box-sizing: border-box; max-height: none; display: inline; line-height: normal; text-align: left; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative; \u3e95 and the authors obtain optimal ratios for various five state systems. For the continuous case, the authors develop various strategies, namely linear, optimal-following, progressive and exponential. The authors show that the best competitive strategies are those that follow the offline schedule in an accelerated manner. Strategy “progressive” consistently produces competitive ratios significantly better than 2

Energy-Delay Tradeoffs of Virtual Base Stations With a Computational-Resource-Aware Energy Consumption Model

The next generation (5G) cellular network faces the challenges of efficiency, flexibility, and sustainability to support data traffic in the mobile Internet era. To tackle these challenges, cloud-based cellular architectures have been proposed where virtual base stations (VBSs) play a key role. VBSs bring further energy savings but also demands a new energy consumption model as well as the optimization of computational resources. This paper studies the energy-delay tradeoffs of VBSs with delay tolerant traffic. We propose a computational-resource-aware energy consumption model to capture the total energy consumption of a VBS and reflect the dynamic allocation of computational resources including the number of CPU cores and the CPU speed. Based on the model, we analyze the energy-delay tradeoffs of a VBS considering BS sleeping and state switching cost to minimize the weighted sum of power consumption and average delay. We derive the explicit form of the optimal data transmission rate and find the condition under which the energy optimal rate exists and is unique. Opportunities to reduce the average delay and achieve energy savings simultaneously are observed. We further propose an efficient algorithm to jointly optimize the data rate and the number of CPU cores. Numerical results validate our theoretical analyses and under a typical simulation setting we find more than 60% energy savings can be achieved by VBSs compared with conventional base stations under the EARTH model, which demonstrates the great potential of VBSs in 5G cellular systems.Comment: 5 pages, 3 figures, accepted by ICCS'1

Lagrangian Duality based Algorithms in Online Energy-Efficient Scheduling

We study online scheduling problems in the general energy model of speed scaling with power down. The latter is a combination of the two extensively studied energy models, speed scaling and power down, toward a more realistic one. Due to the limits of the current techniques, only few results have been known in the general energy model in contrast to the large literature of the previous ones. In the paper, we consider a Lagrangian duality based approach to design and analyze algorithms in the general energy model. We show the applicability of the approach to problems which are unlikely to admit a convex relaxation. Specifically, we consider the problem of minimizing energy with a single machine in which jobs arrive online and have to be processed before their deadlines. We present an alpha^alpha-competitive algorithm (whose the analysis is tight up to a constant factor) where the energy power function is of typical form z^alpha + g for constants alpha > 2 and g non-negative. Besides, we also consider the problem of minimizing the weighted flow-time plus energy. We give an O(alpha/ln(alpha))-competitive algorithm; that matches (up to a constant factor) to the currently best known algorithm for this problem in the restricted model of speed scaling

A low-energy rate-adaptive bit-interleaved passive optical network

Energy consumption of customer premises equipment (CPE) has become a serious issue in the new generations of time-division multiplexing passive optical networks, which operate at 10 Gb/s or higher. It is becoming a major factor in global network energy consumption, and it poses problems during emergencies when CPE is battery-operated. In this paper, a low-energy passive optical network (PON) that uses a novel bit-interleaving downstream protocol is proposed. The details about the network architecture, protocol, and the key enabling implementation aspects, including dynamic traffic interleaving, rate-adaptive descrambling of decimated traffic, and the design and implementation of a downsampling clock and data recovery circuit, are described. The proposed concept is shown to reduce the energy consumption for protocol processing by a factor of 30. A detailed analysis of the energy consumption in the CPE shows that the interleaving protocol reduces the total energy consumption of the CPE significantly in comparison to the standard 10 Gb/s PON CPE. Experimental results obtained from measurements on the implemented CPE prototype confirm that the CPE consumes significantly less energy than the standard 10 Gb/s PON CPE