Una aproximación multinivel para el diseño sistemático de circuitos integrados de radiofrecuencia.

Tesis reducida por acuerdo de confidencialidad.En un mercado bien establecido como el de las telecomunicaciones, donde se está evolucionando hacia el 5G, se estima que hoy en día haya más de 2 Mil Millones de usuarios de Smartphones. Solo de por sí, este número es asombroso. Pero nada se compara a lo que va a pasar en un futuro muy próximo. El próximo boom tecnológico está directamente conectado con el mercado emergente del internet of things (IoT). Se estima que, en 2020, habrá 20 Mil Millones de dispositivos físicos conectados y comunicando entre sí, lo que equivale a 4 dispositivos físicos por cada persona del planeta. Debido a este boom tecnológico, van a surgir nuevas e interesantes oportunidades de inversión e investigación. De hecho, se estima que en 2020 se van a invertir cerca de 3 Mil Millones de dólares solo en este mercado, un 50% más que en 2017. Todos estos dispositivos IoT tienen que comunicarse inalámbricamente entre sí, algo en lo que los circuitos de radiofrecuencia (RF) son imprescindibles. El problema es que el diseño de circuitos RF en tecnologías nanométricas se está haciendo extraordinariamente difícil debido a su creciente complejidad. Este hecho, combinado con los críticos compromisos entre las prestaciones de estos circuitos, tales como el consumo de energía, el área de chip, la fiabilidad de los chips, etc., provocan una reducción en la productividad en su diseño, algo que supone un problema debido a las estrictas restricciones time-to-market de las empresas. Es posible concluir, por tanto, que uno de los ámbitos en los que es tremendamente importante centrarse hoy en día, es el desarrollo de nuevas metodologías de diseño de circuitos RF que permitan al diseñador obtener circuitos que cumplan con especificaciones muy exigentes en un tiempo razonable. Debido a las complejas relaciones entre prestaciones de los circuitos RF (por ejemplo, ruido de fase frente a consumo de potencia en un oscilador controlado por tensión), es fácil comprender que el diseño de circuitos RF es una tarea extremadamente complicada y debe ser soportada por herramientas de diseño asistido por ordenador (EDA). En un escenario ideal, los diseñadores tendrían una herramienta EDA que podría generar automáticamente un circuito integrado (IC), algo definido en la literatura como un compilador de silicio. Con esta herramienta ideal, el usuario sólo estipularía las especificaciones deseadas para su sistema y la herramienta generaría automáticamente el diseño del IC listo para fabricar (lo que se denomina diseño físico o layout). Sin embargo, para sistemas complejos tales como circuitos RF, dicha herramienta no existe. La tesis que se presenta, se centra exactamente en el desarrollo de nuevas metodologías de diseño capaces de mejorar el estado del arte y acortar la brecha de productividad existente en el diseño de circuitos RF. Por lo tanto, con el fin de establecer una nueva metodología de diseño para sistemas RF, se han de abordar distintos cuellos de botella del diseño RF con el fin de diseñar con éxito dichos circuitos. El diseño de circuitos RF ha seguido tradicionalmente una estrategia basada en ecuaciones analíticas derivadas específicamente para cada circuito y que exige una gran experiencia del diseñador. Esto significa que el diseñador plantea una estrategia para diseñar el circuito manualmente y, tras varias iteraciones, normalmente logra que el circuito cumpla con las especificaciones deseadas. No obstante, conseguir diseños con prestaciones óptimas puede ser muy difícil utilizando esta metodología, ya que el espacio de diseño (o búsqueda) es enorme (decenas de variables de diseño con cientos de combinaciones diferentes). Aunque el diseñador llegue a una solución que cumpla todas las especificaciones, nunca estará seguro de que el diseño al que ha llegado es el mejor (por ejemplo, el que consuma menos energía). Hoy en día, las técnicas basadas en optimización se están utilizando con el objetivo de ayudar al diseñador a encontrar automáticamente zonas óptimas de diseño. El uso de metodologías basadas en optimización intenta superar las limitaciones de metodologías previas mediante el uso de algoritmos que son capaces de realizar una amplia exploración del espacio de diseño para encontrar diseños de prestaciones óptimas. La filosofía de estas metodologías es que el diseñador elige las especificaciones del circuito, selecciona la topología y ejecuta una optimización que devuelve el valor de cada componente del circuito óptimo (por ejemplo, anchos y longitudes de los transistores) de forma automática. Además, mediante el uso de estos algoritmos, la exploración del espacio de diseño permite estudiar los distintos y complejos compromisos entre prestaciones de los circuitos de RF. Sin embargo, la problemática del diseño de RF es mucho más amplia que la selección del tamaño de cada componente. Con el objetivo de conseguir algo similar a un compilador de silicio para circuitos RF, la metodología desarrollada en la tesis, tiene que ser capaz de asegurar un diseño robusto que permita al diseñador tener éxito frente a medidas experimentales, y, además, las optimizaciones tienen que ser elaboradas en tiempos razonables para que se puedan cumplir las estrictas restricciones time-to-market de las empresas. Para conseguir esto, en esta tesis, hay cuatro aspectos clave que son abordados en la metodología: 1. Los inductores integrados todavía son un cuello de botella en circuitos RF. Los parásitos que aparecen a altas frecuencias hacen que las prestaciones de los inductores sean muy difíciles de modelar. Existe, por tanto, la necesidad de desarrollar nuevos modelos más precisos, pero también muy eficientes computacionalmente que puedan ser incluidos en metodologías que usen algoritmos de optimización. 2. Las variaciones de proceso son fenómenos que afectan mucho las tecnologías nanométricas, así que para obtener un diseño robusto es necesario tener en cuenta estas variaciones durante la optimización. 3. En las metodologías de diseño manual, los parásitos de layout normalmente no se tienen en cuenta en una primera fase de diseño. En ese sentido, cuando el diseñador pasa del diseño topológico al diseño físico, puede que su circuito deje de cumplir con las especificaciones. Estas consideraciones físicas del circuito deben ser tenidas en cuenta en las primeras etapas de diseño. Por lo tanto, con el fin de abordar este problema, la metodología desarrollada tiene que tener en cuenta los parásitos de la realización física desde una primera fase de optimización. 4. Una vez se ha desarrollado la capacidad de generar distintos circuitos RF de forma automática utilizando esta metodología (amplificadores de bajo ruido, osciladores controlados por tensión y mezcladores), en la tesis se aborda también la composición de un sistema RF con una aproximación multinivel, donde el proceso empieza por el diseño de los componentes pasivos y termina componiendo distintos circuitos, construyendo un sistema (por ejemplo, un receptor de radiofrecuencia). La tesis aborda los cuatro problemas descritos anteriormente con éxito, y ha avanzado considerablemente en el estado del arte de metodologías de diseño automáticas/sistemáticas para circuitos RF.Premio Extraordinario de Doctorado U

Electromagnetic Interference and Compatibility

Recent progress in the fields of Electrical and Electronic Engineering has created new application scenarios and new Electromagnetic Compatibility (EMC) challenges, along with novel tools and methodologies to address them. This volume, which collects the contributions published in the “Electromagnetic Interference and Compatibility” Special Issue of MDPI Electronics, provides a vivid picture of current research trends and new developments in the rapidly evolving, broad area of EMC, including contributions on EMC issues in digital communications, power electronics, and analog integrated circuits and sensors, along with signal and power integrity and electromagnetic interference (EMI) suppression properties of materials

Monolithically Integrated Acoustic Resonators on CMOS for Radio-Frequency Circuit Applications

Wireless communication circuits rely on the use of high-quality passive elements (inductor-capacitor resonant tanks) for the implementation of selective filters and high-purity frequency references (oscillators). Typically available CMOS, on-chip passives suffer from high losses, primarily inductors, and consume large areas that cannot be populated by transistors leading to a significant area penalty. Mechanical resonators exhibit significantly lower losses than their electrical counterparts due to the reduced parasitic loss mechanisms in the mechanical domain. Efficient transduction schemes such as the piezoelectric effect allow for simple electrical actuation and read-out of such mechanical resonators. Piezoelectric thin-film bulk acoustic resonators (FBARs) are currently among the most promising and widely used mechanical resonator structures. However, FBARs are currently only available as off-chip components, which must be connected to CMOS circuitry through wire-bonding and flip-chip schemes. The use of off-chip interfaces introduces considerable parasitics and significant limitations on integration density. Monolithic integration with CMOS substrates alleviates interconnect parasitics, increases integration density and allows for area sharing whereby FBARs reside atop active CMOS circuitry. Close integration of FBARs and CMOS transistors can also enable new circuit paradigms, which simultaneously leverage the strengths of both components. Described here, is a body of work conducted to integrate FBAR resonators with active CMOS substrates (180nm and 65nm processes). A monolithic fabrication method is described which allows for FBAR devices to be constructed atop the backend small CMOS dies through low thermal-budget (< 300°C) post-processing. Stand-alone fabricated devices are characterized and the extracted electrical model is used to design two oscillator chips. The chips comprise amplifier circuitry that functions along with the integrated FBARs to achieve oscillation in the 0.8-2 GHz range. The chips also include test structures to assess the performance of the underlying CMOS transistors before and after the resonator post-processing. A successful FBAR-CMOS oscillator is demonstrated in 65nm CMOS along with characterization of FBARs built on CMOS. The approach presented here can be used for experimenting with more complex circuits leveraging the co-integration of piezoelectric resonators and CMOS transistors

Matlab

This book is a collection of 19 excellent works presenting different applications of several MATLAB tools that can be used for educational, scientific and engineering purposes. Chapters include tips and tricks for programming and developing Graphical User Interfaces (GUIs), power system analysis, control systems design, system modelling and simulations, parallel processing, optimization, signal and image processing, finite different solutions, geosciences and portfolio insurance. Thus, readers from a range of professional fields will benefit from its content

Advanced Modeling, Control, and Optimization Methods in Power Hybrid Systems - 2021

The climate changes that are becoming visible today are a challenge for the global research community. In this context, renewable energy sources, fuel cell systems and other energy generating sources must be optimally combined and connected to the grid system using advanced energy transaction methods. As this reprint presents the latest solutions in the implementation of fuel cell and renewable energy in mobile and stationary applications such as hybrid and microgrid power systems based on the Energy Internet, blockchain technology and smart contracts, we hope that they will be of interest to readers working in the related fields mentioned above

Circuit Design

Circuit Design = Science + Art! Designers need a skilled "gut feeling" about circuits and related analytical techniques, plus creativity, to solve all problems and to adhere to the specifications, the written and the unwritten ones. You must anticipate a large number of influences, like temperature effects, supply voltages changes, offset voltages, layout parasitics, and numerous kinds of technology variations to end up with a circuit that works. This is challenging for analog, custom-digital, mixed-signal or RF circuits, and often researching new design methods in relevant journals, conference proceedings and design tools unfortunately gives the impression that just a "wild bunch" of "advanced techniques" exist. On the other hand, state-of-the-art tools nowadays indeed offer a good cockpit to steer the design flow, which include clever statistical methods and optimization techniques.Actually, this almost presents a second breakthrough, like the introduction of circuit simulators 40 years ago! Users can now conveniently analyse all the problems (discover, quantify, verify), and even exploit them, for example for optimization purposes. Most designers are caught up on everyday problems, so we fit that "wild bunch" into a systematic approach for variation-aware design, a designer's field guide and more. That is where this book can help! Circuit Design: Anticipate, Analyze, Exploit Variations starts with best-practise manual methods and links them tightly to up-to-date automation algorithms. We provide many tractable examples and explain key techniques you have to know. We then enable you to select and setup suitable methods for each design task - knowing their prerequisites, advantages and, as too often overlooked, their limitations as well. The good thing with computers is that you yourself can often verify amazing things with little effort, and you can use software not only to your direct advantage in solving a specific problem, but also for becoming a better skilled, more experienced engineer. Unfortunately, EDA design environments are not good at all to learn about advanced numerics. So with this book we also provide two apps for learning about statistic and optimization directly with circuit-related examples, and in real-time so without the long simulation times. This helps to develop a healthy statistical gut feeling for circuit design. The book is written for engineers, students in engineering and CAD / methodology experts. Readers should have some background in standard design techniques like entering a design in a schematic capture and simulating it, and also know about major technology aspects

Two-Dimensional Electronic Materials and Devices: Opportunities and Challenges

The unprecedented growth of the Internet of Things (IoT) and the 4th Industrial Revolution (Industry 4.0) not only demands dimensional scaling of device technologies but also new types of applications beyond today’s electronics. Two-dimensional (2D) materials, a group of layered crystals (such as graphene and MoS2) with unique properties, have emerged as promising candidates for IoT and Industry 4.0 since they can, not only extend the scaling with unprecedented performance and energy efficiency but also exhibit high potential for novel electronic devices. However, such nanomaterials suffer from significant challenges in process integration, especially in the modules that involves the formation of interfaces between 2D materials and conventional bulk materials. Thus, realizing high-performance energy-efficient 2D electronic devices has been challenging. This dissertation focuses on understanding the fundamental issues in such 2D materials (such as contacts, interfaces and doping) and in identifying applications uniquely enabled by these materials.First, a comprehensive treatment of metal contacts to 2D semiconductors, which has been a huge hurdle for 2D electronic technologies, will be presented. As a pioneering study, new interface physics originating from the unique dimensionality and surface properties have been revealed [1]. Solutions to minimize contact resistance are described though techniques of interface hybridization [2] and seamless contacts [3], [4]. These techniques transform 2D semiconductors from solely scientifically-interesting materials into high-performance field-effect transistor (FET) technologies, such as MoS2 FETs with record-low contact resistances [5], [6] and WSe2 FETs with record-high drive current and mobility [7]. Beyond metal interfaces, dielectric interface is crucial for preserving the carrier mobility in 2D channels, for which a solution enabled by buffer layers has been proposed [8]. On the other hand, the vertical van der Waals interfaces between 2D and 3D semiconductors, which retain the advantages of pristine ultra-thin 2D films as well as maximized tunneling area/field, have been studied and exploited into a novel beyond-silicon transistor technology – the first 2D channel tunnel FET (TFET) [9], which beat the fundamental limitation in the switching behavior of transistors. Recent results from the engineering of such 2D-3D semiconductor interfaces by surface reduction/passivation are described, showing a significant boost of drive current. While conventional diffusion/ion implantation methods are infeasible for 2D materials, two efficient doping techniques that are specific for 2D materials – surface doping [10], [11] and intercalation doping [12] are presented. The theoretical study of surface doping using ab-initio methods helped develop a novel doping scheme that uniquely exploits the Lewis-base like pedigree of 2D semiconductors without disturbing the structural integrity of the 2D atomic layer configuration [13], as well as a novel electrocatalyst based on MoS2 that achieved record high hydrogen evolution reaction (HER) performance [14]. On the other hand, intercalation doping has been employed to demonstrate graphene based transparent electrodes with the best combination of transmittance and sheet resistance [12], and also the first graphene interconnects with excellent performance, reliability and energy-efficiency [15], [16]. Moreover, by uniquely exploiting the high kinetic inductance and conductivity of intercalation doped graphene, a fundamentally different on-chip inductor has been demonstrated [17], [18], with both small form-factors and high inductance values, that were once thought unachievable in tandem. This 2D technique provides an attractive solution to the longstanding scaling problem of analog/radio-frequency electronics and opens up an unconventional pathway for the development of future ultra-compact wireless communication systems. Finally, a novel dissipative quantum transport methodology based on Büttiker probes with band-to-band tunneling capability is developed for 2D FETs [19]. Subsequently, gate-induced-drain-leakage (GIDL), one of the main leakage mechanisms in FETs especially access transistors, is evaluated for the first time for 2D FETs. The results establish the advantages of certain 2D semiconductors in greatly reducing GIDL and thereby support use of such materials in future memory technologies.The dissertation concludes with a vision for how a smart life can be realized in the future by harnessing the capabilities of various 2D technologies in the era of IoT and Industry 4.0.[1] J. Kang, D. Sarkar, W. Liu, D. Jena, and K. Banerjee, “A computational study of metal-contacts to beyond-graphene 2D semiconductor materials,” in IEEE International Electron Devices Meeting, 2012, pp. 407–410.[2] J. Kang, W. Liu, D. Sarkar, D. Jena, and K. Banerjee, “Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors,” Phys. Rev. X, vol. 4, no. 3, p. 31005, Jul. 2014.[3] J. Kang, D. Sarkar, Y. Khatami, and K. Banerjee, “Proposal for all-graphene monolithic logic circuits,” Appl. Phys. Lett., vol. 103, no. 8, p. 83113, 2013.[4] A. Allain, J. Kang, K. Banerjee, and A. Kis, “Electrical contacts to two-dimensional semiconductors,” Nat. Mater., vol. 14, no. 12, pp. 1195–1205, 2015.[5] W. Liu et al., “High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance,” in IEEE International Electron Devices Meeting, 2013, pp. 499–502.[6] J. Kang, W. Liu, and K. Banerjee, “High-performance MoS2 transistors with low-resistance molybdenum contacts,” Appl. Phys. Lett., vol. 104, no. 9, p. 93106, Mar. 2014.[7] W. Liu, J. Kang, D. Sarkar, Y. Khatami, D. Jena, and K. Banerjee, “Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors.,” Nano Lett., vol. 13, no. 5, pp. 1983–90, May 2013.[8] J. Kang, W. Liu, and K. Banerjee, “Computational Study of Interfaces between 2D MoS2 and Surroundings,” in 45th IEEE Semiconductor Interface Specialists Conference, 2014.[9] D. Sarkar et al., “A subthermionic tunnel field-effect transistor with an atomically thin channel,” Nature, vol. 526, no. 7571, pp. 91–95, Sep. 2015.[10] Y. Khatami, W. Liu, J. Kang, and K. Banerjee, “Prospects of graphene electrodes in photovoltaics,” in Proceedings of SPIE, 2013, vol. 8824, p. 88240T–88240T–6.[11] D. Sarkar et al., “Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing,” Nano Lett., vol. 15, no. 5, pp. 2852–2862, May 2015.[12] W. Liu, J. Kang, and K. Banerjee, “Characterization of FeCl3 intercalation doped CVD few-layer graphene,” IEEE Electron Device Lett., vol. 37, no. 9, pp. 1246–1249, Sep. 2016.[13] S. Lei et al., “Surface functionalization of two-dimensional metal chalcogenides by Lewis acid–base chemistry,” Nat. Nanotechnol., vol. 11, no. 5, pp. 465–471, Feb. 2016.[14] J. Li, J. Kang, Q. Cai, W. Hong, C. Jian, and W. Liu, “Boosting Hydrogen Evolution Performance of MoS2 by Band Structure Engineering,” Adv. Mater. Interfaces, vol. 1700303, 2017.[15] J. Jiang et al., “Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects,” Nano Lett., vol. 17, no. 3, pp. 1482–1488, Mar. 2017.[16] J. Jiang, J. Kang, and K. Banerjee, “Characterization of Self - Heating and Current - Carrying Capacity of Intercalation Doped Graphene - Nanoribbon Interconnects,” in IEEE International Reliability Physics Symposium, 2017, p. 6B.1.1-6B.1.6.[17] X. Li et al., “Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect,” in IEEE International Electron Devices Meeting, 2014, p. 5.4.1-5.4.4.[18] J. Kang et al., under review.[19] J. Kang et al., under review

Integrated Circuit Design for Radiation Sensing and Hardening.

Beyond the 1950s, integrated circuits have been widely used in a number of electronic devices surrounding people’s lives. In addition to computing electronics, scientific and medical equipment have also been undergone a metamorphosis, especially in radiation related fields where compact and precision radiation detection systems for nuclear power plants, positron emission tomography (PET), and radiation hardened by design (RHBD) circuits for space applications fabricated in advanced manufacturing technologies are exposed to the non-negligible probability of soft errors by radiation impact events. The integrated circuit design for radiation measurement equipment not only leads to numerous advantages on size and power consumption, but also raises many challenges regarding the speed and noise to replace conventional design modalities. This thesis presents solutions to front-end receiver designs for radiation sensors as well as an error detection and correction method to microprocessor designs under the condition of soft error occurrence. For the first preamplifier design, a novel technique that enhances the bandwidth and suppresses the input current noise by using two inductors is discussed. With the dual-inductor TIA signal processing configuration, one can reduce the fabrication cost, the area overhead, and the power consumption in a fast readout package. The second front-end receiver is a novel detector capacitance compensation technique by using the Miller effect. The fabricated CSA exhibits minimal variation in the pulse shape as the detector capacitance is increased. Lastly, a modified D flip-flop is discussed that is called Razor-Lite using charge-sharing at internal nodes to provide a compact EDAC design for modern well-balanced processors and RHBD against soft errors by SEE.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111548/1/iykwon_1.pd