NASA Technology Plan 1998

This NASA Strategic Plan describes an ambitious, exciting vision for the Agency across all its Strategic Enterprises that addresses a series of fundamental questions of science and research. This vision is so challenging that it literally depends on the success of an aggressive, cutting-edge advanced technology development program. The objective of this plan is to describe the NASA-wide technology program in a manner that provides not only the content of ongoing and planned activities, but also the rationale and justification for these activities in the context of NASA's future needs. The scope of this plan is Agencywide, and it includes technology investments to support all major space and aeronautics program areas, but particular emphasis is placed on longer term strategic technology efforts that will have broad impact across the spectrum of NASA activities and perhaps beyond. Our goal is to broaden the understanding of NASA technology programs and to encourage greater participation from outside the Agency. By relating technology goals to anticipated mission needs, we hope to stimulate additional innovative approaches to technology challenges and promote more cooperative programs with partners outside NASA who share common goals. We also believe that this will increase the transfer of NASA-sponsored technology into nonaerospace applications, resulting in an even greater return on the investment in NASA

Tactical Electronics Simulation Test System: Final Report CDRL A004

Report addresses the preliminary findings of the Tactical Electronics Simulation Test System (TESTS) Phase I effort: Requirements Analysis and Feasibility Assessment, involving requirements for an advanced identification friend or foe (IFF) simulation environment, existing applicable and available facilities and resources for subsequent project phases, technical issues and concerns to minimize risk, and technical approach and conceptual design for an advanced IFF system and environment simulation leading to TESTS

1995 BRAC Commission

Air Force/Army - Site Visit Presentations, May 1995. Presentations to the Commission by Air Force and Army facilities during May 1995. Box 86, L-008

High Level Synthesis of Neural Network Chips

This thesis investigates the development of a silicon compiler dedicated to generate Application-Specific Neural Network Chips (ASNNCs) from a high level C-based behavioural specification language. The aim is to fully integrate the silicon compiler with the ESPRIT II Pygmalion neural programming environment. The integration of these two tools permits the translation of a neural network application specified in nC, the Pygmalion's C-based neural programming language, into either binary (for simulation) or silicon (for execution in hardware). Several applications benefit from this approach, in particular the ones that require real-time execution, for which a true neural computer is required. This research comprises two major parts: extension of the Pygmalion neural programming environment, to support automatic generation of neural network chips from the nC specification language; and implementation of the high level synthesis part of the neural silicon compiler. The extension of the neural programming environment has been developed to adapt the nC language to hardware constraints, and to provide the environment with a simulation tool to test in advance the performance of the neural chips. Firstly, new hardware-specific requisites have been incorporated to nC. However, special attention has been taken to avoid transforming nC into a hardware-oriented language, since the system assumes minimum (or even no) knowledge of VLSI design from the application developer. Secondly, a simulator for neural network hardware has been developed, which assesses how well the generated circuit will perform the neural computation. Lastly, a hardware library of neural network models associated with a target VLSI architecture has been built. The development of the neural silicon compiler focuses on the high level synthesis part of the process. The goal of the silicon compiler is to take nC as the input language and automatically translate it into one or more identical integrated circuits, which are specified in VHDL (the IEEE standard hardware description language) at the register transfer level. The development of the high level synthesis comprises four major parts: firstly, compilation and software-like optimisations of nC; secondly, transformation of the compiled code into a graph-based internal representation, which has been designed to be the basis for the hardware synthesis; thirdly, further transformations and hardware-like optimisations on the internal representation; and finally, creation of the neural chip's data path and control unit that implement the behaviour specified in nC. Special attention has been devoted to the creation of optimised hardware structures for the ASNNCs employing both phases of neural computing on-chip: recall and learning. This is achieved through the data path and control synthesis algorithms, which adopt a heuristic approach that targets the generated hardware structure of the neural chip in a specific VLSI architecture, namely the Generic Neuron. The viability, concerning the effective use of silicon area versus speed, has been evaluated through the automatic generation of a VHDL description for the neural chip employing the Back Propagation neural network model. This description is compared with the one created manually by a hardware designer