506 research outputs found
A 12-bit, 40 msamples/s, low-power, low-area pipeline analog-to-digital converter in CMOS 0.18 mum technology.
With advancements in digital signal processing in recent years, the need for high-speed, high-resolution analog-to-digital converters (ADCs) which can be used in the analog front-end has been increasing. Some examples of these applications are image and video signal processing, wireless communications and asymmetrical digital subscriber line (ADSL). In CMOS integrated circuit design, it is desirable to integrate the digital circuit and the ADC in one microchip to reduce the cost of fabrication. Consequently the power dissipation and area of the ADCs are important design factors. The original contributions in this thesis are as follows. Since the performance of pipeline ADCs significantly depends on the op-amps and comparators circuits, the performance of various comparators is analyzed and the effect of op-amp topology on the performance of pipeline ADCs is investigated. This thesis also presents a novel architecture for design of low-power and low-area pipelined ADCs which will be more useful for very low voltage applications in the future. At the schematic level, a low-power CMOS implementation of the current-mode MDAC is presented and an improved voltage comparator is designed. With the proposed design and the optimization methodology it is possible to reduce power dissipation and area compared with conventional fully differential schemes.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .M64. Source: Masters Abstracts International, Volume: 43-01, page: 0281. Adviser: C. Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004
Carbon footprint of 3D-printed bone tissue engineering scaffolds: an life cycle assessment study
The bone tissue engineering scaffolds is one of the
methods for repairing bone defects caused by various factors.
According to modern tissue engineering technology,
three-dimensional (3D) printing technology for bone tissue
engineering provides a temporary basis for the creation of
biological replacements. Through the generated 3D bone tissue
engineering scaffolds from previous studies, the assessment to
evaluate the environmental impact has shown less attention in
research. Therefore, this paper is aimed to propose the Model of
life cycle assessment (LCA) for 3D bone tissue engineering
scaffolds of 3D gel-printing technology and presented the
analysis technique of LCA from cradle-to-gate for assessing the
environmental impacts of carbon footprint. Acrylamide
(C3H5NO), citric acid (C6H8O7), N,N-Dimethylaminopropyl
acrylamide (C8H16N2O), deionized water (H2O), and
2-Hydroxyethyl acrylate (C5H8O3) was selected as the material
resources. Meanwhile, the 3D gel-printing technology was used
as the manufacturing processes in the system boundary. The
analysis is based on the LCA Model through the application of
GaBi software. The environmental impact was assessed in the
3D gel-printing technology and it was obtained that the system
shows the environmental impact of global warming potential
(GWP). All of the emissions contributed to GWP have been
identified such as emissions to air, freshwater, seawater, and
industrial soil. The aggregation of GWP result in the stage of
manufacturing process for input and output data contributed
47.6% and 32.5% respectively. Hence, the data analysis of the
results is expected to use for improving the performance at the
material and manufacturing process of the product life cycle
A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter
This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes. The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF)
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