RF CMOS quadrature voltage-controlled oscillator design using superharmonic coupling method.

Chung, Wai Fung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.Includes bibliographical references (leaves 98-100).Abstracts in English and Chinese.摘要 --- p.IIIACKNOWLEDGEMENT --- p.IVCONTENTS --- p.VLIST OF FIGURES --- p.VIIILIST OF TABLES --- p.XLIST OF TABLES --- p.XChapter CHAPTER 1 --- INTRODUCTION --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Receiver Architecture --- p.3Chapter 1.2.1 --- Zero-IF Receivers --- p.4Chapter 1.2.2 --- Low-IF Receivers --- p.6Chapter 1.2.2.1 --- Hartley Architecture --- p.7Chapter 1.2.2.2 --- Weaver Architecture --- p.9Chapter 1.3 --- Image-rejection ratio --- p.10Chapter 1.4 --- Thesis Organization --- p.12Chapter CHAPTER 2 --- FUNDAMENTALS OF OSCILLATOR --- p.13Chapter 2.1 --- Basic Oscillator Theory --- p.13Chapter 2.2 --- Varactor --- p.15Chapter 2.3 --- Inductor --- p.17Chapter 2.4 --- Phase noise --- p.22Chapter 2.4.1 --- The Leeson ´ةs phase noise expression --- p.24Chapter 2.4.2 --- Linear model --- p.25Chapter 2.4.3 --- Linear Time-Variant phase noise model --- p.28Chapter CHAPTER 3 --- FULLY-INTEGRATED CMOS OSCILLATOR DESIGN --- p.31Chapter 3.1 --- Ring oscillator --- p.31Chapter 3.2 --- LC oscillator --- p.33Chapter 3.2.1 --- LC-tank resonator --- p.34Chapter 3.2.2 --- Negative transconductance --- p.36Chapter 3.3 --- Generation of quadrature phase signals --- p.39Chapter 3.4 --- Quadrature VCO topologies --- p.41Chapter 3.4.1 --- Parallel-coupled QVCO --- p.41Chapter 3.4.2 --- Series-coupled QVCO --- p.46Chapter 3.4.3 --- QVCO with Back-gate Coupling --- p.47Chapter 3.4.4 --- QVCO using superharmonic coupling --- p.49Chapter 3.5 --- Novel QVCO using back-gate superharmonic coupling --- p.52Chapter 3.5.1 --- Tuning range --- p.54Chapter 3.5.2 --- Negative gm --- p.55Chapter 3.5.3 --- Phase noise calculation --- p.56Chapter 3.5.4 --- Coupling coefficient --- p.57Chapter 3.5.5 --- Low-voltage and low-power design --- p.59Chapter 3.5.6 --- Layout Consideration --- p.61Chapter 3.5.6.1 --- Symmetrical Layout and parasitics --- p.61Chapter 3.5.6.2 --- Metal width and number of vias --- p.63Chapter 3.5.6.3 --- Substrate contact and guard ring --- p.63Chapter 3.5.7 --- Simulation Results --- p.65Chapter 3.5.7.1 --- Frequency and output power --- p.65Chapter 3.5.7.2 --- Quadrature signal generation --- p.67Chapter 3.5.7.3 --- Tuning range --- p.67Chapter 3.5.7.4 --- Power consumption --- p.68Chapter 3.5.7.5 --- Phase noise --- p.69Chapter 3.6 --- Polyphase filter and Single-sideband mixer design --- p.70Chapter 3.6.1 --- Polyphase filter --- p.72Chapter 3.6.2 --- Layout Consideration --- p.74Chapter 3.6.3 --- Simulation results --- p.76Chapter 3.7 --- Comparison with parallel-coupled QVCO --- p.78Chapter CHAPTER 4 --- EXPERIMENTAL RESULTS --- p.80Chapter 4.1 --- Test Fixture --- p.82Chapter 4.2 --- Measurement set-up --- p.84Chapter 4.3 --- Measurement results --- p.86Chapter 4.3.1 --- Proposed QVCO using back-gate superharmonic coupling --- p.86Chapter 4.3.1.1 --- Output Spectrum --- p.86Chapter 4.3.1.2 --- Tuning range --- p.87Chapter 4.3.1.3 --- Phase noise --- p.88Chapter 4.3.1.4 --- Power consumption --- p.88Chapter 4.3.1.5 --- Image-rejection ratio --- p.89Chapter 4.3.2 --- Parallel-coupled QVCO --- p.90Chapter 4.3.2.1 --- Output spectrum --- p.90Chapter 4.3.2.2 --- Power consumption --- p.90Chapter 4.3.2.3 --- Tuning range --- p.91Chapter 4.3.2.4 --- Phase noise --- p.92Chapter 4.3.3 --- Comparison between proposed and parallel-coupled QVCO --- p.93Chapter CHAPTER 5 --- CONCLUSIONS --- p.95Chapter 5.1 --- Conclusions --- p.95Chapter 5.2 --- Future work --- p.97REFERENCES --- p.9

A Wideband Quadrature VCO Using a Novel Tail Current-Clipping Technique

This thesis presents a Quadrature VCO (QVCO) architecture using a novel tail current-clipping technique that improves the phase noise performance of a traditional QVCO by about 4 dB while obtaining a tuning range of about 4 to 5 GHz. This work introduces an innovative idea based on a new approach of implementing a QVCO without an explicit conventional parallel or series coupling network and eliminates some of the issues associated with a traditional QVCO such as bimodal oscillations and phase noise degradation due to the coupling network. The proposed structure has a lot of advantages over the traditional P-QVCO in terms of both phase noise and power consumption. The proposed QVCO was fabricated in the 40 nm CMOS technology. The measured phase noise at 4.9 GHz was about -123.2 dBc/Hz at 1 MHz offset frequency while the quadrature error was less than 3° over the complete tuning range. The proposed architecture consumes a power of about 7.5 mW from a supply of 1.1 V with a figure-of-merit (FoM) of 188.27 dBc/Hz at 4.9 GHz output frequency

System-on-Package Low-Power Telemetry and Signal Conditioning unit for Biomedical Applications

Recent advancements in healthcare monitoring equipments and wireless communication technologies have led to the integration of specialized medical technology with the pervasive wireless networks. Intensive research has been focused on the development of medical wireless networks (MWN) for telemedicine and smart home care services. Wireless technology also shows potential promises in surgical applications. Unlike conventional surgery, an expert surgeon can perform the surgery from a remote location using robot manipulators and monitor the status of the real surgery through wireless communication link. To provide this service each surgical tool must be facilitated with smart electronics to accrue data and transmit the data successfully to the monitoring unit through wireless network. To avoid unwieldy wires between the smart surgical tool and monitoring units and to reap the benefit of excellent features of wireless technology, each smart surgical tool must incorporate a low-power wireless transmitter. Low-power transmitter with high efficiency is essential for short range wireless communication. Unlike conventional transmitters used for cellular communication, injection-locked transmitter shows greater promises in short range wireless communication. The core block of an injection-locked transmitter is an injection-locked oscillator. Therefore, this research work is directed towards the development of a low-voltage low-power injection-locked oscillator which will facilitate the development of a low-power injection-locked transmitter for MWN applications. Structure of oscillator and types of injection are two crucial design criteria for low-power injection-locked oscillator design. Compared to other injection structures, body-level injection offers low-voltage and low-power operation. Again, conventional NMOS/PMOS-only cross-coupled LC oscillator can work with low supply voltage but the power consumption is relatively high. To overcome this problem, a self-cascode LC oscillator structure has been used which provides both low-voltage and low-power operation. Body terminal coupling is used with this structure to achieve injection-locking. Simulation results show that the self-cascode structure consumes much less power compared to that of the conventional structure for the same output swing while exhibiting better phase noise performance. Usage of PMOS devices and body bias control not only reduces the flicker noise and power consumption but also eliminates the requirements of expensive fabrication process for body terminal access

Low-power transceiver design for mobile wireless chemical biological sensors

The design of a smart integrated chemical sensor system that will enhance sensor performance and compatibility to Ad hoc network architecture remains a challenge. This work involves the design of a Transceiver for a mobile chemical sensor. The transceiver design integrates all building blocks on-chip, including a low-noise amplifier with an input-matching network, a Voltage Controlled Oscillator with injection locking, Gilbert cell mixers, and a Class E Power amplifier making it as a single-chip transceiver. This proposed low power 2GHz transceiver has been designed in TSMC 0.35~lm CMOS process using Cadence electronic design automation tools. Post layout HSPICE simulation indicates that Design meets the separation of noise levels by 52dB and 42dB in transmitter and receiver respectively with power consumption of 56 mW and 38 mW in transmit and receive mode

Clock Generation Design for Continuous-Time Sigma-Delta Analog-To-Digital Converter in Communication Systems

Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (ΣΔ) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass ΣΔ which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system. Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (ΣΔ) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption. Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz. Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits

Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier

The increasing demand for high data rates in wireless communication systems is increasing the requirements on the transceiver front-ends, as they are pushed to utilize more and wider bands at higher frequencies. The work in this thesis is focused on receiver front-ends composed of Low Noise Amplifiers (LNAs), Mixers, and Voltage Controlled Oscillators (VCOs) operating at microwave frequencies. Traditionally, microwave electronics has used exclusive and more expensive semiconductor technologies (III-V materials). However, the rapid development of consumer electronics (e.g. video game consoles) the last decade has pushed the silicon CMOS IC technology towards even smaller feature sizes. This has resulted in high speed transistors (high fT and fmax) with low noise figures. However, as the breakdown voltages have decreased, a lower supply voltage must be used, which has had a negative impact on linearity and dynamic range. Nonetheless, todays downscaled CMOS technology is a feasible alternative for many microwave and even millimeter wave applications. The low quality factor (Q) of passive components on-chip usually limits the high frequency performance. For inductors realized in a standard CMOS process the substrate coupling results in a degraded Q. The quality factor can, however, be improved by moving the passive components off-chip and integrating them on a low loss carrier. This thesis therefore features microwave front-end and VCO designs in CMOS, where some designs have been flip-chip mounted on carriers featuring high Q inductors and low loss baluns. The thesis starts with an introduction to wireless communication, receiver architectures, front-end receiver blocks, and low loss carrier technology, followed by the included papers. The six included papers show the capability of CMOS and carrier technology at microwave frequencies: Papers II, III, and VI demonstrate fully integrated CMOS circuit designs. An LC-VCO using an accumulation mode varactor is presented in Paper II, a QVCO using 4-bit switched tuning is shown in Paper III, and a quadrature receiver front-end (including QVCO) is demonstrated in paper VI. Papers I and IV demonstrate receiver front-ends using low loss baluns on carrier for the LO and RF signals. Paper IV also includes a front-end using single-ended RF input which is converted to differential form in a novel merged LNA and balun. A VCO demonstrating the benefits of a high Q inductor on carrier is presented in Paper V

A modified multiphase oscillator with improved phase noise performance

This paper investigates the factors that influence the phase noise performance of an oscillator and proposes a modified structure for improved phase noise performance. A single and multiphase oscillator analysis using the harmonic balance method is presented. The modified structure increases the oscillation amplitude without increasing the bias current and leads to improved phase noise performance as well as decreased power consumption. The modification is analyzed and the figure of merit of the oscillator shows a significant improvement of 21 dB. Numerical and analytical solutions are presented to predict the oscillation frequency and phase noise. The analytical solution is used to approximate the first harmonic and can be combined with numerical simulations to extrapolate phase noise performance.The measurements relating to this work were enabled through the support of SAAB Electronic Defence Systems (EDS). Funding was also received from the National Research Foundation (NRF), Department of Science and Technology, South Africa. NRF funding was for measurement equipment – a millimeter-wave vector network analyzer (under grant ID: 72321) and wafer-prober (under grant ID: 78580). NRF funding (under grant ID: 72321) also allowed collaboration with Prof Luca Larcher, Università degli studi di Modena e Reggio Emilia, Italy.http://www.elsevier.com/locate/mejo2018-04-30am2017Electrical, Electronic and Computer Engineerin

350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS

A new enhanced swing class-D VCO which operates from a supply voltage as low as 300 mV is presented. The architectural advantages are described along with an analysis for the oscillation frequency. Prototype differential and quadrature variants of the proposed VCO have been implemented in a 65 nm RF CMOS process with a 5 GHz VCO oscillation frequency. At a 350 mV supply, the measured phase noise performance for the quadrature VCO with a 5% tuning range is -137.1 dBc/Hz at 3 MHz offset with a power dissipation of 2.1 mW from a 0.35 V supply. The highest resulting figure-of-merit (FoM) is 198.3 dBc/Hz.©2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range