Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium

The articles in this special section were presented at the 2019 IEEE VLSI Test Symposium (VTS) that was held in Monterey, CA. The 2019 VTS Conference laid particular emphasis on enlarging its scope by soliciting submissions on testing, reliability, and security aspects on the following hot topics: approximate computing, neuromorphic computing, and quantum computing

Maximum-Likelihood Sequence Detection of Multiple Antenna Systems over Dispersive Channels via Sphere Decoding

Multiple antenna systems are capable of providing high data rate transmissions over wireless channels. When the channels are dispersive, the signal at each receive antenna is a combination of both the current and past symbols sent from all transmit antennas corrupted by noise. The optimal receiver is a maximum-likelihood sequence detector and is often considered to be practically infeasible due to high computational complexity (exponential in number of antennas and channel memory). Therefore, in practice, one often settles for a less complex suboptimal receiver structure, typically with an equalizer meant to suppress both the intersymbol and interuser interference, followed by the decoder. We propose a sphere decoding for the sequence detection in multiple antenna communication systems over dispersive channels. The sphere decoding provides the maximum-likelihood estimate with computational complexity comparable to the standard space-time decision-feedback equalizing (DFE) algorithms. The performance and complexity of the sphere decoding are compared with the DFE algorithm by means of simulations

Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques

Peer reviewe

Computer technology: State of the art and future trends

Computer technology and, more broadly, information technology, are bringing about a fundamental transformation in our society from an industrial economy to an information economy. A review of the short history and present state of information technology identifies two major undercurrents: I) the miniaturization of computer components, which has produced a millionfold increase in the complexity possible in a single chip of silicon, and 2) the integration of four previously separate areas of information technology: computation, communication, databases and the user interface. Microelectronics, computer networks, data storage and user amenities are the basic technologies that support these four areas and stimulate their progress. Future trends in speech recognition, voice synthesis, artificial intelligence, expert systems, computational imaging and scientific workstations are also examined

Pipelined Asynchronous High Level Synthesis for General Programs

High-level synthesis (HLS) translates algorithms from software programming language into hardware. We use the dataflow HLS methodology to translate programs into asynchronous circuits by implementing programs using asynchronous dataflow elements as hardware building blocks. We extend the prior work in dataflow synthesis in the following aspects:i) we propose Fluid to synthesize pipelined dataflow circuits for real-world programs with complex control flows, which are not supported in the previous work; ii) we propose PipeLink to permit pipelined access to shared resources in the dataflow circuit. Dataflow circuit results in distributed control and an implicitly pipelined implementation. However, resource sharing in the presence of pipelining is challenging in this context due to the absence of a global scheduler. Traditional solutions to this problem impose restrictions on pipelining to guarantee mutually exclusive access to the shared resource, but PipeLink removes such restrictions and can generate pipelined asynchronous dataflow circuits for shared function calls, pipelined memory accesses and function pointers; iii) we apply several dataflow optimizations to improve the quality of the synthesized dataflow circuits; iv) we implement our system (Fluid + PipeLink) on the LLVM compiler framework, which allows us to take advantage of the optimization efforts from the compiler community; v) we compare our system with a widely-used academic HLS tool and two commercial HLS tools. Compared to commercial (academic) HLS tools, our system results in 12X (20X) reduction in energy, 1.29X (1.64X) improvement in throughput, 1.27X (1.61X) improvement in latency at a cost of 2.4X (1.61X) increase in the area