3,482 research outputs found
Optimization of ring oscillators
Dissertação para obtenção do Grau de Mestre em
Engenharia Electrotécnica e de ComputadoresVoltage Controlled Oscillators (VCOs) are from all the building blocks of a PLL, those whose implementation is more critical, since the quality of the signal depends on its performance. The VCOs can be implemented based on LC oscillators or ring oscillators. The ring oscillators, despite of being worst when it comes to manners of phase noise, they are rather used due to lower power consumption, wider tuning range and occupying less area.
Despite the fact that VCOs are widely used in last years, their designed is still a problem hard to deal with, since the ring oscillators circuits must satisfy some specifications such as area, power, speed and noise.
The work proposed in this thesis aims at the development of an environment for automatic scaling of voltage-controlled oscillators with ring topology. In this work it was considered a design methodology based optimization using an analytical model of the oscillator. The oscillator model is based on the EKV model for the characterization of the transistors so as to ensure its applicability to submicron dimensions technologies.
The work took place according to the following phases:
- Study of ring oscillators and models proposed in the literature
- Evaluation of the limitations of existing models and proposed use of EKV model.
- Automatic determination of the parameters of the EKV model for UMC130 technology
- Development of an analytic model for characterizing the VCO with predefined delay cell.
- Use of optimization techniques for automatic sizing of the VCO
Downscaling of 0.35 J.lm to 0.25 J.lm CMOS Transistor by Simulation
Silicon (Si) based integrated circuit (IC) has become the backbone of today's semiconductor
world with MOS transistors as its fundamental building blocks. The integrated circuit
complexity has moved from the early small-scale integration (SSI) to ultra-large-scale
integration (ULSI) that can accommodate millions of transistors on a single chip. This
evolution is primarily attributed to the concept of device miniaturization. The resulting scaledown
devices do not only improve the packing density but also exhibit enhanced
performance in terms of faster switching speed and lower power dissipation. The objective of
this work is to perform downscaling of 0.35 Jll11 to 0.25 Jll11 CMOS transistor using Silvaco
2-D ATHENA and ATLAS simulation tool. A "two-step design" approach is proposed in this
work to study the feasibility of miniaturization process by scaling method. A scaling factor, K
of 1.4 (derived from direct division of 0.35 with 0.25) is adopted for selected parameters. The
first design step involves a conversion of the physical data of 0.35 Jll11 CMOS technology to
the simulated environment, where process recipe acquired from UC Berkeley
Microfabrication Lab serves as the design basis. The electrical data for the simulated
structure of 0.35 11m CMOS was extracted with the use of the device simulator. Using the
simulated, optimized 0.35 Jll11 structure, downscaling to a smaller geometry of 0.25 Jll11
CMOS transistor was carried out and subsequent electrical characterization was performed in
order to evaluate its performance. Parameters that are monitored to evaluate the performance
of the designed 0.25 Jll11 CMOS transistor include threshold voltage (VtJJ, saturation current
(ldsaJ, off-state leakage current (Ion) and subthreshold swing (SJ. From the simulation, the V1h
obtained is of 0.51 V and -0.4 V for NMOS and PMOS respectively, with a difference of
15%-33% as compared to other reported work. However, for results of Idsat. the values
obtained which is of 296 ~-tAIJll11 for NMOS and 181 J.lA/Jll11 for PMOS is much lower than
other reported work by 28%-50%. This is believed to be due to direct scaling of 0.25 Jll11
transistor from the 0.35 11m geometry without alterations on the existing structure. For Ioffand
St. both results show a much better value as compared to other work. I off obtained which is of
<1 0 pA/J.lm is about 80%-96% lower than the maximum allowable specification. As for S1,
the values obtained which is <90 mY/dec is only within 5% differences as compared to
specification. In overall, these results (except for Idsat)
accepted values for the particular 0.25 J..Lm technology. From this work, the capability to
perform device miniaturization from 0.35 J..Lffi to 0.25 J..Lffi has been developed. This is
achieved by acquiring the technical know-how on the important aspects of simulation
required for successful simulation of 0.35 J..Lffi technology. Ultimately, the outcome of this
work which is a simulated 0.25 J..Lm CMOS transistor can be used as a basis for scaling down
to a much smaller device, namely towards 90-nrn geometry
NMOS DEVICE OPTIMIZATION AND FABRICATION USING ATHENA & ATLAS SIMULATION SOFTWARE
Experiment has proven that NMOS performs better than PMOS due to higher drive
current, higher mobility, easier to implement scaling technology and low power
consumption. However, there is still room for further optimization as the technology
trend for the miniaturization ofNMOS and integrated devices continue to grow. In
this project, several objectives have been outlined to be completed within 2 semester
period. These include detailed understanding of fabrication aspect and NMOS
properties, optimizing NMOS by reducing threshold voltage, minimizing off-stage
leakage, reducing gate length, increasing switching speed and designing a mixed
mode circuit.
However, the cost required to perform experimental analysis and optimization of
semiconductor devices using fabrication process can be very expensive especially
when involving purchase of expensive electrical testing equipment. Thus, it is
recommended to perform optimization and analysis using simulation. One ofthe best
device process and simulation tool is Silvaco ATHENA & ATLAS simulation
software. It provides user with various capability in process and electrical testing.
After manipulating and improving process parameters, the optimized device has
recorded significant improvement over the predecessor. Optimizations include better
threshold voltage extraction (0.2v), drain current rise beyond pinch off, better drain
current extraction, higher switching speed at 2Ghz, better device structure after ion
implantation due to tilted implantation, lower off-stage leakage current
(1.2589 x 10' A/um) and minimization ofjunction breakdown effect
Course development in IC manufacturing
A traditional curriculum in electrical engineering separates semiconductor processing courses from courses in circuit design. As a result, manufacturing topics involving yield management and the study of random process variations impacting circuit behaviour are usually vaguely treated. The subject matter of this paper is to report a course developed at Texas A&M University, USA, to compensate for the aforementioned shortcoming. This course attempts to link technological process and circuit design domains by emphasizing aspects such as process disturbance modeling, yield modeling, and defect-induced fault modeling. In a rapidly changing environment where high-end technologies are evolving towards submicron features and towards high transistor integration, these aspects are key factors to design for manufacturability. The paper presents the course's syllabus, a description of its main topics, and results on selected project assignments carried out during a normal academic semeste
A design for testability study on a high performance automatic gain control circuit.
A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente
Computer-Assisted Prototyping of Advanced Microsystems
Contains reports on five research projects.Defense Advanced Research Projects Agency Contract DABT 63-95-C-0088Stanford Universit
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