On Certain New Methodology for Reducing Sensor and Readout Electronics Circuitry Noise in Digital Domain

NASA Hubble Space Telescope (HST) and upcoming cosmology science missions carry instruments with multiple focal planes populated with many large sensor detector arrays. These sensors are passively cooled to low temperatures for low-level light (L3) and near-infrared (NIR) signal detection, and the sensor readout electronics circuitry must perform at extremely low noise levels to enable new required science measurements. Because we are at the technological edge of enhanced performance for sensors and readout electronics circuitry, as determined by thermal noise level at given temperature in analog domain, we must find new ways of further compensating for the noise in the signal digital domain. To facilitate this new approach, state-of-the-art sensors are augmented at their array hardware boundaries by non-illuminated reference pixels, which can be used to reduce noise attributed to sensors. There are a few proposed methodologies of processing in the digital domain the information carried by reference pixels, as employed by the Hubble Space Telescope and the James Webb Space Telescope Projects. These methods involve using spatial and temporal statistical parameters derived from boundary reference pixel information to enhance the active (non-reference) pixel signals. To make a step beyond this heritage methodology, we apply the NASA-developed technology known as the Hilbert- Huang Transform Data Processing System (HHT-DPS) for reference pixel information processing and its utilization in reconfigurable hardware on-board a spaceflight instrument or post-processing on the ground. The methodology examines signal processing for a 2-D domain, in which high-variance components of the thermal noise are carried by both active and reference pixels, similar to that in processing of low-voltage differential signals and subtraction of a single analog reference pixel from all active pixels on the sensor. Heritage methods using the aforementioned statistical parameters in the digital domain (such as statistical averaging of the reference pixels themselves) zeroes out the high-variance components, and the counterpart components in the active pixels remain uncorrected. This paper describes how the new methodology was demonstrated through analysis of fast-varying noise components using the Hilbert-Huang Transform Data Processing System tool (HHT-DPS) developed at NASA and the high-level programming language MATLAB (Trademark of MathWorks Inc.), as well as alternative methods for correcting for the high-variance noise component, using an HgCdTe sensor data. The NASA Hubble Space Telescope data post-processing, as well as future deep-space cosmology projects on-board instrument data processing from all the sensor channels, would benefit from this effort

A novel readout method for focal plane array imaging in the presence of large dark current

This research was an investigation of a novel readout method for focal plane array (FPA) optical imaging, especially for very sensitive detectors with large dark current. The readout method is based on periodically blocking the optical input enabling the removal of the dark current integration from the output. The research demonstrated that it is feasible to modulate the optical input with the designed readout circuit and thus achieve longer signal integration time to enhance the signal-to-noise ratio. Study of a proposed circuit model showed that in theory the correlated readout method could increase the output voltage swing and reduce the noise level by attenuating low frequency noise, thereby effectively improving the FPA dynamic range. Circuits based on standard CMOS circuitry were designed, simulated by PSpice, fabricated using Orbit 2µm n-well technology, and tested with a PI-4000 system. In the circuit evaluation, the output noise due to the clock switching phenomena, the gate signal feedthrough and the charge relaxation, was considered to be the critical problem. The most promising design for minimizing this problem had a CMOS current steering circuit at the input of a high CMRR operational amplifier. Simulation and test results showed that a modified capacitive transimpedance amplifier (CTIA) could subtract dark current output and reduce the output signal due to any difference between the frequencies of the optical input modulation signal and the switch modulation signal. In conclusion, the correlated readout circuit was shown to be a promising approach for advancing FPA technology

INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

Wiring Nanoscale Biosensors with Piezoelectric Nanomechanical Resonators

Nanoscale integrated circuits and sensors will require methods for unobtrusive interconnection with the macroscopic world to fully realize their potential. We report on a nanoelectromechanical system that may present a solution to the wiring problem by enabling information from multisite sensors to be multiplexed onto a single output line. The basis for this method is a mechanical Fourier transform mediated by piezoelectrically coupled nanoscale resonators. Our technique allows sensitive, linear, and real-time measurement of electrical potentials from conceivably any voltage-sensitive device. With this method, we demonstrate the direct transduction of neuronal action potentials from an extracellular microelectrode. This approach to wiring nanoscale devices could lead to minimally invasive implantable sensors with thousands of channels for in vivo neuronal recording, medical diagnostics, and electrochemical sensing

Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones

Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits and data converters based on frequency-encoding. This research has been motivated by the needs of consumer electronics industry, which constantly demands more compact readout circuit for MEMS microphones and other sensors. Nowadays, data acquisition is mainly based on encoding signals in voltage or current domains, which is becoming more challenging in modern deep submicron CMOS technologies. Frequency-encoding is an emerging signal processing technique based on encoding signals in the frequency domain. The key advantage of this approach is that systems can be implemented using mostly-digital circuitry, which benefits from CMOS technology scaling. Frequencyencoding can be used to build phase referenced integrators, which can replace classical integrators (such as switched-capacitor based integrators) in the implementation of efficient analog-to-digital converters and sensor interfaces. The core of the phase referenced integrators studied in this thesis consists of the combination of different oscillator topologies with counters and highly-digital circuitry. This work addresses two related problems: the development of capacitive MEMS sensor readout circuits based on frequency-encoding, and the design and implementation of compact oscillator-based data converters for audio applications. In the first problem, the target is the integration of the MEMS sensor into an oscillator circuit, making the oscillation frequency dependent on the sensor capacitance. This way, the sound can be digitized by measuring the oscillation frequency, using digital circuitry. However, a MEMS microphone is a complex structure on which several parasitic effects can influence the operation of the oscillator. This work presents a feasibility analysis of the integration of a MEMS microphone into different oscillator topologies. The conclusion of this study is that the parasitics of the MEMS limit the performance of the microphone, making it inefficient. In contrast, replacing conventional ADCs with frequency-encoding based ADCs has proven a very efficient solution, which motivates the next problem. In the second problem, the focus is on the development of high-order oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical integrators and phase referenced integrators has been studied, followed by an overview of state-of-art oscillator-based converters. Then, a procedure to replace classical integrators by phase referenced integrators is presented, including a design example of a second-order oscillator based Sigma-Delta modulator. Subsequently, the main circuit impairments that limit the performance of this kind of implementations, such as phase noise, jitter or metastability, are described. This thesis also presents a methodology to evaluate the impact of phase noise and distortion in oscillator-based systems. The proposed method is based on periodic steady-state analysis, which allows the rapid estimation of the system dynamic range without resorting to transient simulations. In addition, a novel technique to analyze the impact of clock jitter in Sigma-Delta modulators is described. Two integrated circuits have been implemented in 0.13 μm CMOS technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder noise shaping using only oscillators and digital circuitry. The first testchip shows a malfunction in the digital circuitry due to the complexity of the multi-bit counters. The second chip, implemented using single-bit counters for simplicity, shows second-order noise shaping and reaches 103 dB-A of dynamic range in the audio bandwidth, occupying only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces para sensores capacitivos basados en codificación en frecuencia. Esta investigación está motivada por las necesidades de la industria, que constantemente demanda reducir el tamaño de este tipo de circuitos. Hoy en día, la adquisición de datos está basada principalmente en la codificación de señales en tensión o en corriente. Sin embargo, la implementación de este tipo de soluciones en tecnologías CMOS nanométricas presenta varias dificultades. La codificación de frecuencia es una técnica emergente en el procesado de señales basada en codificar señales en el dominio de la frecuencia. La principal ventaja de esta alternativa es que los sistemas pueden implementarse usando circuitos mayoritariamente digitales, los cuales se benefician de los avances de la tecnología CMOS. La codificación en frecuencia puede emplearse para construir integradores referidos a la fase, que pueden reemplazar a los integradores clásicos (como los basados en capacidades conmutadas) en la implementación de conversores analógico-digital e interfaces de sensores. Los integradores referidos a la fase estudiados en esta tesis consisten en la combinación de diferentes topologías de osciladores con contadores y circuitos principalmente digitales. Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos de lectura para sensores MEMS capacitivos basados en codificación temporal, y el diseño e implementación de conversores de datos compactos para aplicaciones de audio basados en osciladores. En el primer caso, el objetivo es la integración de un sensor MEMS en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos en su mayor parte digitales. Sin embargo, un micrófono MEMS es una estructura compleja en la que múltiples efectos parasíticos pueden alterar el correcto funcionamiento del oscilador. Este trabajo presenta un análisis de la viabilidad de integrar un micrófono MEMS en diferentes topologías de oscilador. La conclusión de este estudio es que los parasíticos del MEMS limitan el rendimiento del micrófono, causando que esta solución no sea eficiente. En cambio, la implementación de conversores analógico-digitales basados en codificación en frecuencia ha demostrado ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente problema. La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado la equivalencia entre los integradores clásicos y los integradores referidos a la fase, seguido de una descripción de los conversores basados en osciladores publicados en los últimos años. A continuación se presenta un procedimiento para reemplazar integradores clásicos por integradores referidos a la fase, incluyendo un ejemplo de diseño de un modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente se describen los principales problemas que limitan el rendimiento de este tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad. Esta tesis también presenta un nuevo método para evaluar el impacto del ruido de fase y de la distorsión en sistemas basados en osciladores. El método propuesto está basado en simulaciones PSS, las cuales permiten la rápida estimación del rango dinámico del sistema sin necesidad de recurrir a simulaciones temporales. Además, este trabajo describe una nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta. En esta tesis se han implementado dos circuitos integrados en tecnología CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han sido diseñados para producir conformación espectral de ruido de segundo orden, usando únicamente osciladores y circuitos mayoritariamente digitales. El primer chip ha mostrado un error en el funcionamiento de los circuitos digitales debido a la complejidad de las estructuras multi-bit utilizadas. El segundo chip, implementado usando contadores de un solo bit con el fin de simplificar el sistema, consigue conformación espectral de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus

A VCO-based CMOS readout circuit for capacitive MEMS microphones

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered 'always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta (SigmaDelta) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1/𝑓 and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 muA at 1.8 V and the effective area is 0.12 mm2. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.This research was funded by project TEC2017-82653-R of CICYT, Spain