DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

A Low-Cost Unified Experimental FPGA Board for Cryptography Applications

This paper describes the evaluation of available experimental boards, the comparison of their supported set of experiments and other aspects. The second part of this evaluation is focused on the design process of the PCB (Printed Circuit Board) for an FPGA (Field Programmable Gate Array) based cryptography environment suitable for evaluating the latest trends in the IC (Integrated Circuit) security like Side–Channel Attacks (SCA) or Physically Unclonable Function (PUF). It leads to many criteria affecting the design process and also the suitability for evaluating and measuring results of the attacks and their countermeasures. The developed system should be open, versatile and unrestricted by the U.S. law [1]

Industrial and technical aspects of chip embedding technology

Embedding of semiconductor chips into organic substrates allows a very high degree of miniaturization by stacking multiple layers of embedded components, superior electrical performance by short and geometrically well controlled interconnects as well as a homogeneous mechanical environment of the chips, resulting in good reliability. At PCB manufacturing level, 50 mum thin chips have been embedded with pitches up to 200 mum in up to 18ldquotimes24rdquo panels. Embedding of chips at 100 mum pitch has been achieved at prototype level. Further developments of chip embedding can extend to even finer pitches without redistribution methods only with concurrent developments in ultra fine line patterning, plating methods and chemistries, assembly machines. New manufacturing processes should combine PCB processing and die assembly in one production line in order to benefit the most from this combination without the difficulties of transport between different manufacturing plants. Furthermore, new testing methodologies will be developed and a new supply chain will be created due to incorporation of embedding technologies to PCB production. This paper discusses in detail the technology and manufacturing challenges arisen from the integration of embedding technologies to PCB manufacturing processes

Infrastructure for Detector Research and Development towards the International Linear Collider

The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

Investigating SRAM PUFs in large CPUs and GPUs

Physically unclonable functions (PUFs) provide data that can be used for cryptographic purposes: on the one hand randomness for the initialization of random-number generators; on the other hand individual fingerprints for unique identification of specific hardware components. However, today's off-the-shelf personal computers advertise randomness and individual fingerprints only in the form of additional or dedicated hardware. This paper introduces a new set of tools to investigate whether intrinsic PUFs can be found in PC components that are not advertised as containing PUFs. In particular, this paper investigates AMD64 CPU registers as potential PUF sources in the operating-system kernel, the bootloader, and the system BIOS; investigates the CPU cache in the early boot stages; and investigates shared memory on Nvidia GPUs. This investigation found non-random non-fingerprinting behavior in several components but revealed usable PUFs in Nvidia GPUs.Comment: 25 pages, 6 figures. Code in appendi

Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modeling (XRD/3DSM) for non-destructive analysis of manufacturing process-induced stress/warpage inside completely encapsulated packaged chips. The technique is demonstrated at room temperature and at elevated temperatures up to 115C by in situ XRD annealing experiments. The feasibility of this technique is confirmed through the charactersation of die stress inside encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing proces

Devices Having Compliant Wafer-level Input/output Interconnections And Packages Using Pillars And Methods Of Fabrication Thereof

Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed of a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.Georgia Tech Research Corporatio

High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

Y2K Interruption: Can the Doomsday Scenario Be Averted?

The management philosophy until recent years has been to replace the workers with computers, which are available 24 hours a day, need no benefits, no insurance and never complain. But as the year 2000 approached, along with it came the fear of the millennium bug, generally known as Y2K, and the computers threatened to strike!!!! Y2K, though an abbreviation of year 2000, generally refers to the computer glitches which are associated with the year 2000. Computer companies, in order to save memory and money, adopted a voluntary standard in the beginning of the computer era that all computers automatically convert any year designated by two numbers such as 99 into 1999 by adding the digits 19. This saved enormous amount of memory, and thus money, because large databases containing birth dates or other dates only needed to contain the last two digits such as 65 or 86. But it also created a built in flaw that could make the computers inoperable from January 2000. The problem is that most of these old computers are programmed to convert 00 (for the year 2000) into 1900 and not 2000. The trouble could therefore, arise when the systems had to deal with dates outside the 1900s. In 2000, for example a programme that calculates the age of a person born in 1965 will subtract 65 from 00 and get -65. The problem is most acute in mainframe systems, but that does not mean PCs, UNIX and other computing environments are trouble free. Any computer system that relies on date calculations must be tested because the Y2K or the millennium bug arises because of a potential for “date discontinuity” which occurs when the time expressed by a system, or any of its components, does not move in consonance with real time. Though attention has been focused on the potential problems linked with change from 1999 to 2000, date discontinuity may occur at other times in and around this period.