(Invited) mm-wave silicon ICs: An opportunity for holistic design

Millimeter-waves integrated circuits offer a unique opportunity for a holistic design approach encompassing RF, analog, and digital, as well as radiation and electromagnetics. The ability to deal with the complete system from the digital circuitry to on-chip antennas and everything in between offers unparalleled opportunities for completely new architectures and topologies, previously impossible due the traditional partitioning of various blocks in conventional design. This opens a plethora of new architectural and system level innovation within the integrated circuit platform. This paper reviews some of the challenges and opportunities for mm-wave ICs and presents several solutions to them

Device modelling for bendable piezoelectric FET-based touch sensing system

Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point. The potential solutions for high-performance related challenges bring us back to the timetested silicon based electronics. However, the changes in the response of silicon based devices due to bending related stresses is a concern, especially because there are no suitable models to predict this behavior. This also makes the circuit design a difficult task. This paper reports advances in this direction, through our research on bendable Piezoelectric Oxide Semiconductor Field Effect Transistor (POSFET) based touch sensors. The analytical model of POSFET, complimented with Verilog-A model, is presented to describe the device behavior under normal force in planar and stressed conditions. Further, dynamic readout circuit compensation of POSFET devices have been analyzed and compared with similar arrangement to reduce the piezoresistive effect under tensile and compressive stresses. This approach introduces a first step towards the systematic modeling of stress induced changes in device response. This systematic study will help realize high-performance bendable microsystems with integrated sensors and readout circuitry on ultra-thin chips (UTCs) needed in various applications, in particular, the electronic skin (e-skin)

Impact of atomistic device variability on analogue circuit design

Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC

Discrete and Integrated Solutions for Hybrid PV Plants Without Momentary Cessation in Low SCR and High Penetration PE Grids

With the increased penetration of power electronic (PE) based loads and sources, advanced solutions may be required for the enhancement of grid stability in regions with low short circuit ratio (SCR) and high penetration PE grids. The requirement of advanced solutions arises from the gradual paradigm shift of the electric grid from the traditional electric machine dominant system to a high penetration of PE-based system. One of the major challenges with such systems in recent times is the momentary cessation during alternating current (ac) grid transmission faults. During momentary cessation, PE-based resources cease to operate, thus creating probable reliability challenges for the grid. In this paper, potential feasible options to provide continuity of operation during such scenarios are presented. The options are considered through identifying upgrades in existing and upcoming discrete development of photovoltaic (PV) and energy storage systems (ESS) termed as discrete hybrid PV plants. Additionally, an advanced concept of integrated development of PV and ESS connecting to ac transmission grid links called multi-port autonomous reconfigurable solar power plant (MARS) is evaluated. The developed new solutions are evaluated for different grid use cases and scenarios in PSCAD

Circuit Design for Predictive Maintenance

Industry 4.0 has become a driver for the entire manufacturing industry. Smart systems have enabled 30% productivity increases and predictive maintenance has been demonstrated to provide a 50% reduction in machine downtime. So far, the solution has been based on data analytics which has resulted in a proliferation of sensing technologies and infrastructure for data acquisition, transmission and processing. At the core of factory operation and automation are circuits that control and power factory equipment, innovative circuit design has the potential to address many system integration challenges. We present a new circuit design approach based on circuit level artificial intelligence solutions, integrated within control and calibration functional blocks during circuit design, improving the predictability and adaptability of each component for predictive maintenance. This approach is envisioned to encourage the development of new EDA tools such as automatic digital shadow generation and product lifecycle models, that will help identification of circuit parameters that adequately define the operating conditions for dynamic prediction and fault detection. Integration of a supplementary artificial intelligence block within the control loop is considered for capturing non-linearities and gain/bandwidth constraints of the main controller and identifying changes in the operating conditions beyond the response of the controller. System integration topics are discussed regarding integration within OPC Unified Architecture and predictive maintenance interfaces, providing real-time updates to the digital shadow that help maintain an accurate, virtual replica model of the physical system.Comment: 4 pages, 4 figures, position pape

Technology Agnostic Analysis and Design for Improved Performance, Variability, and Reliability in Thin Film Photovoltaics

Thin film photovoltaics (TFPV) offer low cost alternatives to conventional crystalline Silicon (c-Si) PV, and can enable novel applications of PV technology. Their large scale adoption however, requires significant improvements in process yield, and operational reliability. In order to address these challenges, comprehensive understanding of factors affecting panel yield, and predictive models of performance reliability are needed. This has proved to be especially challenging for TFPV for two reasons in particular. First, TFPV technologies encompass a wide variety of materials, processes, and structures, which fragments the research effort. Moreover, the monolithic manufacturing of TFPV modules differs significantly from that of c-Si technology, and requires new integrated approaches to analysis and design for these technologies. In this thesis, we identify a number of features affecting the variability and reliability of TFPV technologies in general, and propose technology agnostic design solutions for improved performance, yield, and lifetime of TFPV modules. We first discuss the universal features of current conduction in TFPV cells, for both intrinsic dark and light currents, and parasitic (shunt) leakage. We establish the universal physics of space-charge-limited shunt conduction in TFPV technologies, and develop physics based compact model for TFPV cells. We examine the statistics of parasitic shunting, and demonstrate its universal log-normal distribution across different technologies. We also evaluate the degradation behavior of cells under reverse bias stress, and identify different degradation mechanisms for intrinsic and parasitic components. We then embed the physics and statistics of cell operation and degradation, in a circuit simulation framework to analyze module performance and reliability. With this integrated circuit-device simulation, we establish log-normal shunt statistics as a major cause of module efficiency loss in TFPV, and develop a in-line technique for module efficiency and yield enhancement. Finally, we study the features of TFPV module reliability under partial shading using this circuit simulation, and propose a geometrical design solution for shade tolerant TFPV modules. The most important theme of this thesis is to establish that TFPV technologies share many universal performance, variability, and reliability challenges. And, by using a technology agnostic approach for studying these problems, we can achieve fruitful cross coupling of ideas and enable broadly applicable solutions for important technological challenges in TFPV

Design Techniques of Highly Integrated Hybrid-Switched-Capacitor-Resonant Power Converters for LED Lighting Applications

The Light-emitting diodes (LEDs) are rapidly emerging as the dominant light source given their high luminous efficacy, long lift span, and thanks to the newly enacted efficiency standards in favor of the more environmentally-friendly LED technology. The LED lighting market is expected to reach USD 105.66 billion by 2025. As such, the lighting industry requires LED drivers, which essentially are power converters, with high efficiency, wide input/output range, low cost, small form factor, and great performance in power factor, and luminance flicker. These requirements raise new challenges beyond the traditional power converter topologies. On the other hand, the development and improvement of new device technologies such as printed thin-film capacitors and integrated high voltage/power devices opens up many new opportunities for mitigating such challenges using innovative circuit design techniques and solutions. Almost all electric products needs certain power delivery, regulation or conversion circuits to meet the optimized operation conditions. Designing a high performance power converter is a real challenge given the market’s increasing requirements on energy efficiency, size, cost, form factor, EMI performance, human health impact, and so on. The design of a LED driver system covers from high voltage AC/DC and DC/DC power converters, to high frequency low voltage digital controllers, to power factor correction (PFC) and EMI filtering techniques, and to safety solutions such as galvanic isolation. In this thesis, we study design challenges and present corresponding solutions to realize highly integrated and high performance LED drivers combining switched-capacitor and resonant converters, applying re-configurable multi-level circuit topology, utilizing sigma delta modulation, and exploring capacitive galvanic isolation. A hybrid switched-capacitor-resonant (HSCR) LED driver based on a stackable switched-capacitor (SC) converter IC rated for 15 to 20 W applications. Bulky transformers have been replaced with a SC ladder to perform high-efficiency voltage step-down conversion; an L-C resonant output network provides almost lossless current regulation and demonstrates the potential of capacitive galvanic isolation. The integrated SC modules can be stacked in the voltage domain to handle a large range of input voltage ranges that largely exceed the voltage limitation of the medium-voltage-rated 120 V silicon technology. The LED driver demonstrates > 91% efficiency over a rectified input DC voltage range from 160 VDC to 180 VDC with two stacked ICs; using a stack of four ICs > 89.6% efficiency is demonstrated over an input range from 320 VDC to 360 VDC . The LED driver can dim its output power to around 10% of the rated power while maintaining >70% efficiency with a PWM controlled clock gating circuit. Next, the design of AC main rectifier and inverter front end with sigma delta modulation is described. The proposed circuits features a pair of sigma delta controlled multilevel converters. The first is a multilevel rectifier responsible for PFC and dimming. The second is a bidirectional multilevel inverter used to cancel AC power ripple from the DC bus. The system also contains an output stage that powers the LEDs with DC and provides for galvanic isolation. Its functional performance indicates that integrated multilevel converters are a viable topology for lighting and other similar applications

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design