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Circuits and architectures for broadband spectrum channelizers with sub-band gain control
Broadband receiver architectures for full-band or concurrent multi-band reception of signals are required in several applications. One approach to implementing such receivers is a spectrum channelizer that employs a frequency-folded analog-to-digital converter (FF-ADC). The design downconverts and channelizes a broadband input signal into multiple sub-bands at baseband by employing the harmonics of non-overlapping rectangular clocks. The downconverted and aliased baseband signal in each path is digitized by a baseband ADC, referred to as a sub-ADC below, that operates with a sampling rate that is lower than the Nyquist sampling rate set by the full bandwidth of the input signal. Sub-band separation is performed through digital harmonic rejection (HR) and image rejection (IR). The design operates similar to a time-interleaved ADC, except that it significantly reduces the bandwidth requirement of the samplers. If rectangular pulse waveforms are used in the FF-ADC down-converter, all sub-bands experience nearly equal gain during frequency down-conversion. Since all sub-bands are aliased to baseband before they are separated in the digital domain, a sub-band with large relative power can reduce the sub-ADC dynamic range that is available for other sub-bands, in addition to appearing as a blocker for other sub-bands. The research presented in this dissertation addresses approaches to overcome this issue, by embedding sub-band gain control within an FF-ADC.
Chapter 2 proposes an approach that employs pulse-width-modulated local oscillator (PWM-LO) waveforms in the polyphase paths of an FF-ADC for scaling individual sub-band signal levels at baseband before digitization. The PWM-LO waveforms, which directly drive switches in each path, can be used to vary the gain in each sub-band by varying the level of harmonics in the waveforms. This is achieved by controlling the pulse-widths of the PWM-LO waveforms. This design avoids the requirement for N ×N switch matrices and variable transconductance cells in prior demonstrated approaches. The proposed architecture makes it possible to vary the spectral response of the FF-ADC with low signal-path complexity. Prediction of pulse widths for the desired harmonic, and hence the gain profile across all sub-bands, is performed using an off-chip supervised learning approach employing a neural network.
Chapter 3 presents the implementation of a spectrum channelizer employing the PWM-LO-based sub-band amplitude control. The design allows for scaling the relative gain of the sub-bands over a 20-dB range. This relaxes the compression performance of the channelizer baseband and the sub-ADC dynamic range in the presence of sub-bands with significantly higher signal levels. Gain control on individual sub-bands is performed by employing customized PWM-LO waveforms,where the PWM-LO pulses are generated using delay-locked loops (DLLs). The off-chip neural-network based learning technique for estimating the PWM symbol pulse widths required for setting the desired LO harmonic levels is described. A 1.6 GS/s spectrum channelizer IC is implemented in a 65-nm CMOS process to verify the architecture. The measured channelizer gain is 51.6-56.5 dB without gain scaling and provides a range of 37-59 dB with PWM-LO gain control. Gain-scaling at a specific harmonic improves blocker compression in an unattenuated sub-band from -34 dBm to -16 dBm. The in-band gain compression with gain-scaling also increases from -32 dBm to -17 dBm.
Chapter 4 describes a spectrum channelizer that uses voltage-mode downconversion. The approach requires a single voltage-mode input amplifier to drive the downconversion switches. Frequency-folding and sub-band gain control are achieved in a single signal path. This contrasts with the current-mode approach that requires a main FF-ADC path and a separate auxiliary path for sub-band gain control. By avoiding the requirement for an auxiliary input path, the approach presented here significantly simplifies the signal chain with identical gain-scaling capability.
The contributions of this research and scope for future related work are summarized in Chapter 5.Electrical and Computer Engineerin
The design of a fully balanced current–tunable active RC integrator
The design of the active RC integrator presented in this research utilizes a fully balanced technique and current-tunable frequencies to create the active RC integrator and reliable circuit. The circuit is made up of six npn bipolar junction transistors (BJT), six resistors (R), and a capacitor (C), with the fully balanced technique used to make the circuit structure uncomplicated and symmetrical with signal differencing. This approach results in a low number of internal devices in the circuit, making it an attractive option for integrated circuit (IC) development. One of the key features of the fully balanced current-tunable active RC integrator is its ability to be frequency-tunable with bias current (If). This feature enables the circuit to be used in a variety of applications, including filter circuits, communication signal generators, instrumentation signal generators, and various automatic controls. The fully balanced design also ensures that the circuit is stable and robust, even in the presence of device parameter variations. To evaluate the performance of the active RC integrator, simulations were conducted using Pspice.
The results show that a fully current-tunable active RC integrator can be precisely tuned with the active bias to a value consistent with the theoretically calculated value. This demonstrates the efficiency and reliability of the circuit design and simulation method. The Monte Carlo (MC) method was also used to analyze the circuit performance in cases where the resistor (R) and capacitor (C) device had a 10 percent error and the transistor gain (β) was set to an error of 50 percent. The MC analysis showed that the phase shift (degree) and magnitude (dB) of the circuit were stable, and the circuit's performance was not significantly impacted by the device parameter variations. This further demonstrates the robustness and versatility of the fully balanced current-tunable active RC integrator design. Finally, harmonic distortion was evaluated to confirm the performance of the designed and developed fully balanced current-tunable active RC integrator. The results showed low levels of harmonic distortion, which indicates that the circuit is suitable for high-performance applications that require low distortio
Design and implementation of a wideband sigma delta ADC
Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTƩ∆M), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications.
The objective of this thesis is to design and implement a wideband CTƩ∆M for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTƩ∆M, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADC’s sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB.
This thesis focuses on the design and implementation of the CTƩ∆M, building upon the principles of a discrete time Ʃ∆ modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTƩ∆ modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTƩ∆ modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTƩ∆M.
The CTƩ∆Ms employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulator’s performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. Tiivistelmä. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistä tärkeämmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnän kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTƩ∆M), joissa käytetään ylinäytteistystä ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun.
Tämän työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjärjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTƩ∆M, jolla on 15MHz:n signaalikaistanleveys. Ylinäytteistyssuhde on 25 ja AD muuntimen näytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR).
Tämä työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Ʃ∆-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmä esitetään yksityiskohtaisesti, ja vaatimusten täyttyminen varmistetaan “top-down” -suunnitteluperiaatteella. Liitteenä on kertoimien laskemiseen käytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkän silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentä -DA muunninta. Viivekompensointipolkua käyttämällä modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. Lisäksi FIR takaisinkytkentä -DA-muuntimen käyttö pienentää kellojitteriherkkyyttä, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyä ja luotettavuutta.
Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty peräkkäin integraattoreita myötäkytkentärakenteella (CIFF) ja toisessa sekä myötä- että takaisinkytkentärakenteella (CIFF-B). Päähuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa käyttäen 0.8 voltin käyttöjännitettä. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. Lisäksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin
D-Band downconversion mixer design in CMOS-SOI
Abstract. The current surge in research interest around the sub-THz frequency region comes as a no surprise. The potential for greater data rates and available bandwidths are just a couple reasons why research around these frequencies should be prioritized. Many viable receiver structures have been presented for these frequency regions, but they all have one thing in common: They all include a downconversion mixer. The mixer is a crucial piece in the receiver structure, converting the higher frequency radio frequency (RF) signal to a much lower intermediate frequency (IF) signal using multiplication with a local oscillator (LO) signal. The resulting waveform is much easier to handle for signal processing that comes after. The downconversion should be able to provide a fair amount of gain to the converted signal on a wide range of input signals, measured with the 1dB compression point. The noise figure is also a major consideration for RF-devices, but in the case of the mixer, its importance is not as prevalent as it is for the LNA that precedes it, since the noise of the mixer is attenuated by the gain of the previous stages.
This master’s thesis work introduces the basic theory around downconversion mixers, followed by the design of a mixer from schematic level circuit design all the way to the physical layout. The physical design is done using 22nm FDSOI technology, provided by GlobalFoundries. The design is made for a direct conversion receiver using Gilbert cell topology, meaning image rejection is reasonable and depends only on the received signal itself, and good noise and feedthrough performance should be expected in simulations. The mixer is to downconvert a 151 GHz signal down to 0–1 GHz, using an LO signal between 150–151 GHz. Two iterations of the mixer are shown in the end results, the first one being based on the schematic design, and the second one with adjustments made for better performance. While driving a high impedance 500 Ohm load, the second iteration was able to reach a conversion gain of -10.0 dB with a 1dB compression point of 6.4 dBm while dissipating 4.7 mW of power. DSB noise figure was simulated to be 17.3 dB and the LO leakage to the IF output at -27.7 dBm.Alaspäin taajuusmuuntavan sekoittimen suunnittelu D-kaistalle käyttäen CMOS-SOI teknologiaa. Tiivistelmä. Nykyinen tutkimuksen keskittyminen millimetriaalto ja THz taajuusalueille ei tule kenellekään yllätyksenä. Suurempien datanopeuksien ja vapaiden taajuuskaistojen potentiaali ovat vain joitain monista hyvistä käytännön syistä, miksi tutkimusta näiden taajuuksien ympärillä priorisoidaan. Monia käytännöllisiä vastaanotinrakenteita on esitetty näille taajuusalueille ja niillä on kaikilla yksi yhteinen tekijä: tajuusmuunnin alemmille taajuuksille. Taajuusmuunnin eli sekoitin on olennainen osa vastaanotinrakenteita, muuntaen korkeamman radiotaajuuden (RF) matalammalle välitaajuudelle (IF) käyttäen taajuuksien sekoittamista paikallisoskillaattorilla (LO). Mikserin ulostulosignaali on signaalinprosessoinnin näkökulmasta paljon käytännöllisempi. Alaspäin taajuusmuuntavan mikserin tulee pystyä vahvistamaan laajaa skaalaa erivahvuisia signaaleja, minkä ylärajaa mittaamme 1 dB kompressiopisteellä. Radiolaitteistossa kohinaluku tulee yleensä myös ottaa huomioon, mutta johtuen mikserin sijainnista vastaanotinketjussa, kohinaluku vaimenee suhteessa sitä edeltävien vahvistuksien verran, eikä siksi ole niin kriittinen.
Tämä diplomityö esittelee lukijalle ensiksi alaspäin muuntavan taajuussekoittimen perusteorian, toisena sen teoreettisen piirikaavion suunnittelun sekä sen simuloinnin tuloksia, ja viimeisenä fyysisen layoutin suunnittelun sekä sen simuloinnin tulokset. Fyysisen layoutin suunnittelu ja simulointi tehdään käyttäen GlobalFoundries 22nm FDSOI teknologiaa. Suunnittelu tehdään suoramuunnosvastaanottimelle käyttäen Gilbertin solu topologiaa, eliminoiden peilitaajuuksista aiheutuvat ongelmat, sekä vähentäen kohinan sekä ei-haluttujen signaalien läpivuotojen vaikutusta. Sekoittimen tulee muuntaa 151 GHz signaali n. 0–1 GHz kantataajuudelle käyttäen LO-signaalia taajuusvälillä 150–151 GHz. Lopullisissa tuloksissa vertaillaan kahta eri iteraatiota. Ensimmäisenä versiota, joka luotiin alun perin teoriapohjaisen piirisuunnittelun pohjalta, sekä toista versiota, missä useilla parannuksilla mikserin suorituskykyä saatiin parannettua. Korkeaimpedanssista 500 Ohmin kuormaa ajaessa mikseri ylsi -10.0 dB vahvistukseen, 1 dB kompressiopiste oli 6.4 dB kuluttaen 4.7 mW virtaa käytössä. Kohinaluvuksi simuloitiin 17.3 dB, sekä LO signaalin vuodosta IF lähtöön oli -27.7 dBm
LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES
The research work described in this thesis was focused on finding novel techniques to
implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit
technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG
signal and several bio-medical signals are sensed from the human body through a pair
of electrodes. The electrical characteristics of the very small amplitude (1u-10mV)
signals are corrupted by random noise and have a significant dc offset. 50/60Hz power
supply coupling noise is one of the biggest cross-talk signals compared to the thermally
generated random noise. These signals are even AFE composed of an Instrumentation
Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main
function of the AFE is to convert the weak electrical Signal into large signals whose
amplitude is large enough for an Analog Digital Converter (ADC) to detect without having
any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal
amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver
needs an accurate and temperature-independent reference voltage and current for the
ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to
consume as low power as possible to enable these circuits to be powered from the
battery.
The work started with analysing the existing circuit techniques for the circuits
mentioned above and finding the key important improvements required to reach the
target specifications. Previously proposed IA is generated based on voltage mode signal
processing. To improve the CMRR (119dB), we proposed a current mode-based IA with
an embedded DC cancellation technique. State-of-the-art VGA circuits were built based
on the degeneration principle of the differential pair, which will enable the variable gain
purpose, but none of these techniques discussed linearity improvement, which is very
important in modern CMOS technologies. This work enhances the total Harmonic
distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around
the differential pair. Also, this work proposes a low power curvature compensated
bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a
1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and
simulated with all the performance metrics with Cadence (spectre) simulator. The circuit
layout was carried out to study post-layout parasitic effect sensitivity
Modeling and Design of High-Performance DC-DC Converters
The goal of the research that was pursued during this PhD is to eventually facilitate the
development of high-performance, fast-switching DC-DC converters. High-switching
frequency in switching mode power supplies (SMPS) can be exploited by reducing the
output voltage ripple for the same size of passives (mainly inductors and capacitors) and
improve overall system performance by providing a voltage supply with less unwanted
harmonics to the subsystems that they support. The opposite side of the trade-off is
also attractive for designers as the same amount of ripple can be achieved with smaller
values of inductance and/or capacitance which can result in a physically smaller and
potentially cheaper end product. Another benefit is that the spectrum of the resulting
switching noise is shifted to higher frequencies which in turn allows designers to push
the corner frequency of the control loop of the system higher without the switching
noise affecting the behavior of the system. This in turn, is translated to a system capable
of responding faster to strong transients that are common in modern systems that may
contain microprocessors or other electronics that tend to consume power in bursts and
may even require the use of features like dynamic voltage scaling to minimize the overall
consumption of the system.
While the analysis of the open loop behavior of a DC-DC converter is relatively
straightforward, it is of limited usefulness as they almost always operate in closed loop
and therefore can suffer from degraded stability. Therefore, it is important to have a
way to simulate their closed loop behavior in the most efficient manner possible. The
first chapter is dedicated to a library of technology-agnostic high-level models that can
be used to improve the efficiency of transient simulations without sacrificing the ability
to model and localize the different losses.
This work also focuses further in fixed-frequency converters that employ Peak Current
Mode Control (PCM) schemes. PCM schemes are frequently used due to their
simple implementation and their ability to respond quickly to line transients since any
change of the battery voltage is reflected in the slope of the rising inductor current
which in turn is monitored by a fast internal control loop that is closed with the help of
a current sensor.
Most existing models for current sensors assume that they behave in an ideal manner
with infinite bandwidth and ideal constant gain. These assumptions tend to be in
significant error as the minimum on-time of the sensor and therefore the settling time
requirements of the sensor are reduced. Some sensing architectures, like the ones that
approximate the inductor current with the high-side switch current, can be even more
complex to analyze as they require the use of extended masking time to prevent spike
currents caused by the switch commutation to be injected to the output of the sensor
and therefore the signal processing blocks of the control loop. In order to solve this issue,
this work also proposes a current sensor model that is compatible with time averaged
models of DC-DC converters and is able to predict the effects of static and transient
non-idealities of the block on the behavior of a PCM DC-DC converter.
Lastly, this work proposes a new 40 V, 6 A, fully-integrated, high-side current sensing
circuit with a response time of 51 . The proposed sensor is able to achieve this
performance with the help of a feedback resistance emulation technique that prevents
the sensor from debiasing during its masking phase which tends to extend the response
time of similar fully integrated sensors
Electrical design of Switched-Capacitor second-order high-Q low-pass filter with channel multiplexing
The aim of this thesis is to design a discrete-time second-order low-pass filter with channel multiplexing for the electronic stability control system. The purpose of this design is to study the current and noise behavior of the multiplexed discrete-time design in comparison to a single-channel continuous-time design. This work discusses the importance of a discrete-time analog filter topology over continuous time in context of integrated area, cost and complexity. It argues about the selection of a ladder-type switched-capacitor filter for the required application and presents the steps for the design from an equivalent RLC filter. It addresses the component design of the selected topology as well as the operational amplifier design. It also discusses the reasons behind the selection of the folded cascode operational amplifier topology for the design. The clocking sequence for the switched-capacitor switches as well as the channel multiplexing switches is explained. The design is verified with simulations and the results of the essential parameters describing the performance of the design are presented. These parameters include the frequency response of the design, current consumption, noise levels, total harmonic distortion of the output signal, and channel isolation between the multiplexed channels. The work is concluded with an explanation of the results and a discussion on the reasons behind out of specification results. Based on this discussion, future work as well as improvements to the existing designs are suggested
Waveform engineering in integrated harmonic oscillators: analysis and examples
openThe thesis analyzes the effect of the presence of a 2nd harmonic resonance in the differential LC oscillator’s tank, going inside the different effect that it causes on waveform shapes and phase noise improvement, with different mechanisms. The above analysis is carried out considering different known topologies of harmonic oscillators understanding in which topologies the tecnicque gives advantages in terms of final phase noise of the oscillator
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations
This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 mm2 , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively
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