An Efficient Data Structure for Dynamic Two-Dimensional Reconfiguration

In the presence of dynamic insertions and deletions into a partially reconfigurable FPGA, fragmentation is unavoidable. This poses the challenge of developing efficient approaches to dynamic defragmentation and reallocation. One key aspect is to develop efficient algorithms and data structures that exploit the two-dimensional geometry of a chip, instead of just one. We propose a new method for this task, based on the fractal structure of a quadtree, which allows dynamic segmentation of the chip area, along with dynamically adjusting the necessary communication infrastructure. We describe a number of algorithmic aspects, and present different solutions. We also provide a number of basic simulations that indicate that the theoretical worst-case bound may be pessimistic.Comment: 11 pages, 12 figures; full version of extended abstract that appeared in ARCS 201

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Two-dimensional placement compaction using an evolutionary approach: a study

The placement problem of two-dimensional objects over planar surfaces optimizing given utility functions is a combinatorial optimization problem. Our main drive is that of surveying genetic algorithms and hybrid metaheuristics in terms of final positioning area compaction of the solution. Furthermore, a new hybrid evolutionary approach, combining a genetic algorithm merged with a non-linear compaction method is introduced and compared with referenced literature heuristics using both randomly generated instances and benchmark problems. A wide variety of experiments is made, and the respective results and discussions are presented. Finally, conclusions are drawn, and future research is defined

Kompetensi pembimbing syarikat bertauliah Sistem Latihan Dual Nasional (SLDN)

Sistem Latihan Dual Nasional (SLDN) merupakan satu sistem latihan dan usahasama antara sektor awam dan sektor swasta dilaksanakan untuk melahirkan tenaga mahir k-worker selari dengan keperluan industri masa kini untuk membangunkan ekonomi negara. Pihak kerajaan dan syarikat swasta menaja pekerja pilihan mereka sebagai pelatih dalam sistem latihan ini bagi mempertingkatkan kebolehan pekerja mereka. Selain itu, pelatih juga terdiri daripada pelajar yang tidak dapat melanjutkan pelajaran ke mana-mana institusi pengajian tinggi awam mahupun swasta. Sistem ini menjalankan pendekatan day release iaitu pelatih menjalani latihan selama empat hari di industri dan satu hari di institusi latihan atau block release iaitu pelatih menjalani latihan kemahiran di industri empat bulan dan satu bulan di institusi latihan mengikut kesesuaian industri tersebut. Kajian berbentuk deskriptif dijalankan untuk melihat melihat tahap kompetensi pembimbing SLDN. Selain itu juga, kajian ini dijalankan bagi melihat perbezaan terhadap tahap pengetahuan, kemahiran dan sikap pembimbing SLDN berdasarkan jantina. Kajian ini juga dibuat bagi menentukan hubungan kompetensi pembimbing berdasarkan pengalaman bekerja. Penyelidikan tinjauan deskriptif ini menggunakan borang soal selidik sebagai instrumen kajian berskala Likert. Seramai 84 orang responden yang terdiri daripada pembimbing syarikat bertauliah SLDN terlibat di dalam kajian ini. Data dianalisis menggunakan SPSS versi 16.0. Hasil analisis mendapati pembimbing mempunyai pengetahuan yang tinggi di samping kemahiran dan sikap. Keputusan inferensi pula menunjukkan tidak terdapat perbezaan antara tahap pengetahuan, kemahiran dan sikap pembimbing berdasarkan jantina manakala analisis korelasi Pearson menunjukkan tidak terdapat hubungan antara kompetensi pembimbing berdasarkan pengalaman bekerja

Kompetensi pembimbing syarikat bertauliah Sistem Latihan Dual Nasional (SLDN)

Sistem Latihan Dual Nasional (SLDN) merupakan satu sistem latihan dan usahasama antara sektor awam dan sektor swasta dilaksanakan untuk melahirkan tenaga mahir k-worker selari dengan keperluan industri masa kini untuk membangunkan ekonomi negara. Pihak kerajaan dan syarikat swasta menaja pekerja pilihan mereka sebagai pelatih dalam sistem latihan ini bagi mempertingkatkan kebolehan pekerja mereka. Selain itu, pelatih juga terdiri daripada pelajar yang tidak dapat melanjutkan pelajaran ke mana-mana institusi pengajian tinggi awam mahupun swasta. Sistem ini menjalankan pendekatan day release iaitu pelatih menjalani latihan selama empat hari di industri dan satu hari di institusi latihan atau block release iaitu pelatih menjalani latihan kemahiran di industri empat bulan dan satu bulan di institusi latihan mengikut kesesuaian industri tersebut. Kajian berbentuk deskriptif dijalankan untuk melihat melihat tahap kompetensi pembimbing SLDN. Selain itu juga, kajian ini dijalankan bagi melihat perbezaan terhadap tahap pengetahuan, kemahiran dan sikap pembimbing SLDN berdasarkan jantina. Kajian ini juga dibuat bagi menentukan hubungan kompetensi pembimbing berdasarkan pengalaman bekerja. Penyelidikan tinjauan deskriptif ini menggunakan borang soal selidik sebagai instrumen kajian berskala Likert. Seramai 84 orang responden yang terdiri daripada pembimbing syarikat bertauliah SLDN terlibat di dalam kajian ini. Data dianalisis menggunakan SPSS versi 16.0. Hasil analisis mendapati pembimbing mempunyai pengetahuan yang tinggi di samping kemahiran dan sikap. Keputusan inferensi pula menunjukkan tidak terdapat perbezaan antara tahap pengetahuan, kemahiran dan sikap pembimbing berdasarkan jantina manakala analisis korelasi Pearson menunjukkan tidak terdapat hubungan antara kompetensi pembimbing berdasarkan pengalaman bekerja

A survey and taxonomy of layout compaction algorithms

This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential part of modern symbolic layout tools employed in VLSI circuit design. Layout compaction techniques are also used in the low-end stages of silicon compilation tools and module generators. The paper addresses the main algorithms used in compaction, focusing on their implementation characteristics, performance, advantages and drawbacks. Compaction is a highly important operation to optimize the use of silicon area, achieve higher speed through wire length minimization, support technology retargeting and also allow the use of legacy layouts. Optimized cells that were developed for a fabrication process with a set of design rules have to be retargeted for a new and more compact process with a different set of design rules

Solving Irregular Strip Packing Problems With Free Rotations Using Separation Lines

Solving nesting problems or irregular strip packing problems is to position polygons in a fixed width and unlimited length strip, obeying polygon integrity containment constraints and non-overlapping constraints, in order to minimize the used length of the strip. To ensure non-overlapping, we used separation lines. A straight line is a separation line if given two polygons, all vertices of one of the polygons are on one side of the line or on the line, and all vertices of the other polygon are on the other side of the line or on the line. Since we are considering free rotations of the polygons and separation lines, the mathematical model of the studied problem is nonlinear. Therefore, we use the nonlinear programming solver IPOPT (an algorithm of interior points type), which is part of COIN-OR. Computational tests were run using established benchmark instances and the results were compared with the ones obtained with other methodologies in the literature that use free rotation

2D multi-objective placement algorithm for free-form components

This article presents a generic method to solve 2D multi-objective placement problem for free-form components. The proposed method is a relaxed placement technique combined with an hybrid algorithm based on a genetic algorithm and a separation algorithm. The genetic algorithm is used as a global optimizer and is in charge of efficiently exploring the search space. The separation algorithm is used to legalize solutions proposed by the global optimizer, so that placement constraints are satisfied. A test case illustrates the application of the proposed method. Extensions for solving the 3D problem are given at the end of the article.Comment: ASME 2009 International Design Engineering Technical Conferences & Computers and Information in Engineering Conference, San Diego : United States (2009