Adaptive computing’s impact?

Abstract“We're coming upon a sea change in the world of semiconductors,” says Nick Tredennick, former designer of the Motorola 68000 microprocessor, which powered the Apple Mac in the 1980s and early 90s. “There are compelling advantages to reconfigurable chips in terms of performance and power consumption.” The momentum for adaptive computing is a result of advances in special high-speed memory chips called static ram, or S-RAM chips that make it possible to imitate the entire hardware circuits of a processor on a single chip. In adaptive computing, chip wiring would be reconfigured on the fly by software altering the circuitry’s information pathways. Reconfigurable chips may offer speed, cost and energy-saving advantages, and allow for quicker product design cycles. And the ability to combine the functions of many chips into one would be particularly desirable in making smaller, lighter and more energy-efficient portable computing and communications devices. Cellphones that could work worldwide; portable computers that use suitable radio frequency and wirelessly, automatically connect to the Internet, or consumer electronics gadgets able to adjust to each new technical standard in digital sights and sounds, offer enormous attractions with upgrades as easy as downloading the latest circuit design from the Internet. The fixed-circuit approach needs templates, or masks at $1m for each new circuit, making it difficult for product designers to quickly adapt to changing markets and technology formats. But for an adaptive circuit, that investment is not unreasonable. Reconfigurable chip design has several dozen start-ups (eg QuickSilver, and GateChange Technologies), as well interesting the giants. Intel, IBM, Infineon, Motorola and Texas, have all moved into both acquisition and spin-off. Infineon acquired Morphics Technology (reconfigurable circuits for wireless digital telephone networks). Royal Philips Electronics acquired Systemonic, (reconfigurable chips for wireless data applications). Motorola invested in Morpho Technologies (reconfigurable circuits for wireless, imaging and multimedia applications). HP research laboratories has spun off two adaptive companies, Synfora (Program-In Chip-Out PICO) and Elixent (Reconfigurable Algorithm Processing RAP). Reconfigurable looks as if its coming to stay.This is a short news story only. Visit www.three-fives.com for the latest advanced semiconductor industry news

Reconfigurable Security: Edge Computing-based Framework for IoT

In various scenarios, achieving security between IoT devices is challenging since the devices may have different dedicated communication standards, resource constraints as well as various applications. In this article, we first provide requirements and existing solutions for IoT security. We then introduce a new reconfigurable security framework based on edge computing, which utilizes a near-user edge device, i.e., security agent, to simplify key management and offload the computational costs of security algorithms at IoT devices. This framework is designed to overcome the challenges including high computation costs, low flexibility in key management, and low compatibility in deploying new security algorithms in IoT, especially when adopting advanced cryptographic primitives. We also provide the design principles of the reconfigurable security framework, the exemplary security protocols for anonymous authentication and secure data access control, and the performance analysis in terms of feasibility and usability. The reconfigurable security framework paves a new way to strength IoT security by edge computing.Comment: under submission to possible journal publication

ParaFPGA 2011 : high performance computing with multiple FPGAs : design, methodology and applications

ParaFPGA 2011 marks the third mini-symposium devoted to the methodology, design and implementation of parallel applications using FPGAs. The focus of the contributions is mainly on organizing parallel applications in multiple FPGAs. This includes experiences from building a supercomputer with FPGAs, automatic and dedicated balancing of different tasks on heterogeneous FPGA constellations and designing optimal interconnects between collaborating FPGAs

Reconfigurable Mobile Multimedia Systems

This paper discusses reconfigurability issues in lowpower hand-held multimedia systems, with particular emphasis on energy conservation. We claim that a radical new approach has to be taken in order to fulfill the requirements - in terms of processing power and energy consumption - of future mobile applications. A reconfigurable systems-architecture in combination with a QoS driven operating system is introduced that can deal with the inherent dynamics of a mobile system. We present the preliminary results of studies we have done on reconfiguration in hand-held mobile computers: by having reconfigurable media streams, by using reconfigurable processing modules and by migrating functions

Lessons learned from the design of a mobile multimedia system in the Moby Dick project

Recent advances in wireless networking technology and the exponential development of semiconductor technology have engendered a new paradigm of computing, called personal mobile computing or ubiquitous computing. This offers a vision of the future with a much richer and more exciting set of architecture research challenges than extrapolations of the current desktop architectures. In particular, these devices will have limited battery resources, will handle diverse data types, and will operate in environments that are insecure, dynamic and which vary significantly in time and location. The research performed in the MOBY DICK project is about designing such a mobile multimedia system. This paper discusses the approach made in the MOBY DICK project to solve some of these problems, discusses its contributions, and accesses what was learned from the project

MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor

This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented